https://ni.lithium.com/t5/LabVIEW/Getting-timing-errors-while-implementing-the-interleaving-using/m-p/3791752#M1069682 <P>Hi,</P> <P>&nbsp;</P> <P>I have created a&nbsp;'Multistage Multirate Filter'<SPAN> in Labview FPGA using <STRONG>'</STRONG></SPAN>Start IP Generator' . The following link shows the procedure</P> <P>&nbsp;</P> <P><A href="http://zone.ni.com/reference/en-XX/help/371988F-01/lvdfdtconcepts/design_fp_multirate/" target="_blank">http://zone.ni.com/reference/en-XX/help/371988F-01/lvdfdtconcepts/design_fp_multirate/</A></P> <P>&nbsp;</P> <P>When I use the interleaving technique to fill the elements in the filter for multichannel implementation . I get a timing error pertaining to the non block component on FPGA block diagram . Can you please help?</P> <P>&nbsp;</P> <P>Regards</P> Fri, 11 May 2018 05:04:40 GMT Harss 2018-05-11T05:04:40Z https://ni.lithium.com/t5/LabVIEW/Getting-timing-errors-while-implementing-the-interleaving-using/m-p/3791752#M1069682 <P>Hi,</P> <P>&nbsp;</P> <P>I have created a&nbsp;'Multistage Multirate Filter'<SPAN> in Labview FPGA using <STRONG>'</STRONG></SPAN>Start IP Generator' . The following link shows the procedure</P> <P>&nbsp;</P> <P><A href="http://zone.ni.com/reference/en-XX/help/371988F-01/lvdfdtconcepts/design_fp_multirate/" target="_blank">http://zone.ni.com/reference/en-XX/help/371988F-01/lvdfdtconcepts/design_fp_multirate/</A></P> <P>&nbsp;</P> <P>When I use the interleaving technique to fill the elements in the filter for multichannel implementation . I get a timing error pertaining to the non block component on FPGA block diagram . Can you please help?</P> <P>&nbsp;</P> <P>Regards</P> Fri, 11 May 2018 05:04:40 GMT https://ni.lithium.com/t5/LabVIEW/Getting-timing-errors-while-implementing-the-interleaving-using/m-p/3791752#M1069682 Harss 2018-05-11T05:04:40Z