topic Re: Data logging failure... in LabVIEW

Data logging failure...

DNS_MTB — Fri, 03 Jul 2020 01:04:32 GMT

Dear experts...
I am currently trying to collect acceleration sensor data using cRIO-9042 and NI9232 module, but when I run the FPGA code created by referring to the NI homepage, only the input data is 0... (please see the Figture)
If you know the cause or solution of this phenomenon, please reply.
I will attach a VI and a project.
Thank you.

Re: Data logging failure...

Tepig — Thu, 09 Oct 2025 16:08:59 GMT

I guess this is caused by error7. File path "c:\analog_input.tdms" is not valid for Linux-RT.

Please check valid path --> Working with File Paths on Real-Time Targets

Re: Data logging failure...

DNS_MTB — Fri, 03 Jul 2020 05:36:32 GMT

Dear, Emboar.

Thank you very much for your opinion.

I changed the file storage location to'/home/lvuser/test.tdms' by referring to the link you provided, but the same thing happens.

Maybe it's because of another problem.

Thank you.

Re: Data logging failure...

Tepig — Fri, 03 Jul 2020 06:24:49 GMT

Error 7 was removed? Or still there?

Re: Data logging failure...

DNS_MTB — Fri, 03 Jul 2020 06:43:57 GMT

Error 7 is gone, but the data is still only measured as zero...

Thank you.

Re: Data logging failure...

Tepig — Fri, 03 Jul 2020 07:09:36 GMT

On FPGA VI, there is type mismath. Mod2/AI0 is "signed, 24,7" but FPGA FIFO is "signed, 26,5".

Why don't you fix it.

When you directly see the returned FXP value on RT VI, do you also see "ZERO"?

Re: Data logging failure...

crossrulz — Fri, 03 Jul 2020 14:47:48 GMT

What sensor are you using? Do you need to turn on the IEPE for the sensor?

Re: Data logging failure...

DNS_MTB — Fri, 10 Jul 2020 04:36:55 GMT

Sorry, I'm late.

When I looked at the FPGA I/O output as a probe in FPGA.vi, I found the following values:

The meaning of the sentence in the red box is 'not executed'.

And Second figure is current Labview project tree.

What's the problem...??

Re: Data logging failure...

crossrulz — Thu, 09 Oct 2025 16:10:25 GMT

Notice in your project there is a I/O called "Mod2/Start". You need to write a TRUE to this in order to enable the ADC on the module. So write to that IO before your loop.

For more details: NI 9232 (FPGA Interface)

Re: Data logging failure...

DNS_MTB — Wed, 15 Jul 2020 02:34:10 GMT

As you told me, I used 'Mod2/Start', 'Mod2/Stop' block, then It works well !!

Thank you very much.

Have a nice day ^^