topic Re: FPGA compile in LabVIEW

FPGA compile

D.L.ZHANG — Thu, 23 Jun 2022 12:55:51 GMT

when i want to transform image from HOST vi to FPGA traget, something wrong about compile. according the information,I have checked my compile tools, and I do have the vivado 2019.1 edition.i readlly don't know what i could do,so please let me know if anybody konw how to fix this question. the following picture may helpful.thanks for your watching.

Re: FPGA compile

Terry_ALE — Fri, 24 Jun 2022 16:00:58 GMT

I cannot read everything but it looks like the DMA-FIFO datatype in the subVI is different from that of the bitfile.

Re: FPGA compile

D.L.ZHANG — Sat, 25 Jun 2022 03:07:37 GMT

thanks for your reply.

i am a newbie in image processing by FPGA and i have imitated others program in transform image and its lot of error.

so if you get any examples, it's really helpful.

Thanks again

Re: FPGA compile

Terry_ALE — Sat, 25 Jun 2022 12:11:02 GMT

It is not an image issue. It is a LabVIEW FPGA issue.

Can you look inside that subVI in the host and look for a similarly named DMA-FIFO on the FPGA? It is must not have the same datatype.

Re: FPGA compile

Longlong99 — Wed, 03 Aug 2022 13:03:18 GMT

Are you use LabVIEW FPGA version、

Re: FPGA compile

D.L.ZHANG — Mon, 05 Sep 2022 03:29:19 GMT

my labview FPGA version is 2020 edition

Re: FPGA compile

Bob_Schor — Mon, 05 Sep 2022 03:39:38 GMT

For us to understand what you are doing, you will need to attach your entire LabVIEW Project. You should also tell us what version of LabVIEW and what "bitness" you are using, and what is your Remote Target (with the FPGA).

Bob Schor

回复： FPGA compile

Zhaoyuc — Mon, 24 Oct 2022 10:25:08 GMT

Hello Zhang,

I face the same problem with you, could you please tell me how did you solve the problem? I would appreciate it if you could show me your project as a reference.

回复： FPGA compile

D.L.ZHANG — Tue, 25 Oct 2022 01:06:26 GMT

my suggestion is to be sure your FIFO is right, Base on that to compile your FPGA program first. I can not use ISE14.7 in win10 so I change to ues cloud compile tool.

回复： FPGA compile

Zhaoyuc — Tue, 25 Oct 2022 08:27:17 GMT

Thanks for your reply.

I created a same host.vi as you, but got a different error.All my versions of software are 2020, and I set up the FIFO to U8x1 from host to target mode. I show my host.vi and target.vi as follow, could you please give me some suggestions?

回复： FPGA compile

D.L.ZHANG — Thu, 27 Oct 2022 09:18:33 GMT

FIRST, select a FIFO in FPGA program and compile the program.

Second, be sure your RT system program setup is right, especially the IMAQ crate.vi it’s picture style(U8 is default) may not suit for image you transfer.

回复： FPGA compile

Zhaoyuc — Fri, 28 Oct 2022 02:42:53 GMT

Thanks for your reply, but there are still many problems for me, I'll start a new topic to solve these problems.