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    <title>topic Re: FPGA - IQ in LabVIEW</title>
    <link>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/380811#M190801</link>
    <description>Hello,&lt;BR /&gt;
&lt;BR /&gt;
What is the original message in this thread. I've done some signal&lt;BR /&gt;
processing on the IF-RIO using free Xilinx IP cores.&lt;BR /&gt;
&lt;BR /&gt;
Regards,&lt;BR /&gt;
&lt;BR /&gt;
Abhishek&lt;BR /&gt;
&lt;BR /&gt;
&lt;BR /&gt;
Jerry_L wrote:&lt;BR /&gt;
&amp;gt; Hi Troy&lt;BR /&gt;
&amp;gt; I?m not sure if I can answer this question.&amp;amp;nbsp; The way I?ve done it up to now is a FFT and at this point in time, that means on the host computer as one of the NI 5640R examples shows.&amp;amp;nbsp; Unfortunately, I don?t have any FPGA code to implement an FFT algorithm using fixed point math.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; If you post it in the NI 5640R discussion area, someone monitoring the board may have an idea.&amp;amp;nbsp; The method will most likely be tailored to the type of modulation that the signal you are getting is coded in, as well have a guess at the signal?s modulation rate.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; As for "creating a smoothing capacitor mathematically", that is essentially a filter.&amp;amp;nbsp; As of now, there are two methods, using the Digital Filter design Toolkit, or creating one from scratch in fixed point math for the FPGA.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; There are a number of good books in this area.&amp;amp;nbsp; One I recommend is "Understanding Digital Signal Processing" by Richard G. Lyons.&amp;amp;nbsp; The book I have is 1997.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; He also goes into the best description I have read on IQ down conversion / up conversion and the math behind it.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; Jerry&lt;BR /&gt;
&lt;BR /&gt;</description>
    <pubDate>Tue, 20 Jun 2006 11:10:05 GMT</pubDate>
    <dc:creator>abhisheknag</dc:creator>
    <dc:date>2006-06-20T11:10:05Z</dc:date>
    <item>
      <title>FPGA - IQ</title>
      <link>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/379238#M190161</link>
      <description>Are there any resources on the relationship between IQ and frequency.
I'm trying to determine what the frequency of incoming data is, given
it's IQ components.&lt;BR /&gt;
&lt;BR /&gt;
Also, if anyone knows of any resources for creating a smoothing capacitor mathematically, please refer them to me.&lt;BR /&gt;
&lt;DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 15 Jun 2006 15:11:07 GMT</pubDate>
      <guid>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/379238#M190161</guid>
      <dc:creator>troy.perales</dc:creator>
      <dc:date>2006-06-15T15:11:07Z</dc:date>
    </item>
    <item>
      <title>Re: FPGA - IQ</title>
      <link>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/380696#M190754</link>
      <description>&lt;DIV&gt;Hi Troy&lt;/DIV&gt;
&lt;DIV&gt;I’m not sure if I can answer this question.&amp;nbsp; The way I’ve done it up to now is a FFT and at this point in time, that means on the host computer as one of the NI 5640R examples shows.&amp;nbsp; Unfortunately, I don’t have any FPGA code to implement an FFT algorithm using fixed point math.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;If you post it in the NI 5640R discussion area, someone monitoring the board may have an idea.&amp;nbsp; The method will most likely be tailored to the type of modulation that the signal you are getting is coded in, as well have a guess at the signal’s modulation rate.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;As for "creating a smoothing capacitor mathematically", that is essentially a filter.&amp;nbsp; As of now, there are two methods, using the Digital Filter design Toolkit, or creating one from scratch in fixed point math for the FPGA.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;There are a number of good books in this area.&amp;nbsp; One I recommend is "Understanding Digital Signal Processing" by Richard G. Lyons.&amp;nbsp; The book I have is 1997.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;He also goes into the best description I have read on IQ down conversion / up conversion and the math behind it.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Jerry&lt;/DIV&gt;</description>
      <pubDate>Tue, 20 Jun 2006 03:33:02 GMT</pubDate>
      <guid>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/380696#M190754</guid>
      <dc:creator>JerryAL</dc:creator>
      <dc:date>2006-06-20T03:33:02Z</dc:date>
    </item>
    <item>
      <title>Re: FPGA - IQ</title>
      <link>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/380811#M190801</link>
      <description>Hello,&lt;BR /&gt;
&lt;BR /&gt;
What is the original message in this thread. I've done some signal&lt;BR /&gt;
processing on the IF-RIO using free Xilinx IP cores.&lt;BR /&gt;
&lt;BR /&gt;
Regards,&lt;BR /&gt;
&lt;BR /&gt;
Abhishek&lt;BR /&gt;
&lt;BR /&gt;
&lt;BR /&gt;
Jerry_L wrote:&lt;BR /&gt;
&amp;gt; Hi Troy&lt;BR /&gt;
&amp;gt; I?m not sure if I can answer this question.&amp;amp;nbsp; The way I?ve done it up to now is a FFT and at this point in time, that means on the host computer as one of the NI 5640R examples shows.&amp;amp;nbsp; Unfortunately, I don?t have any FPGA code to implement an FFT algorithm using fixed point math.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; If you post it in the NI 5640R discussion area, someone monitoring the board may have an idea.&amp;amp;nbsp; The method will most likely be tailored to the type of modulation that the signal you are getting is coded in, as well have a guess at the signal?s modulation rate.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; As for "creating a smoothing capacitor mathematically", that is essentially a filter.&amp;amp;nbsp; As of now, there are two methods, using the Digital Filter design Toolkit, or creating one from scratch in fixed point math for the FPGA.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; There are a number of good books in this area.&amp;amp;nbsp; One I recommend is "Understanding Digital Signal Processing" by Richard G. Lyons.&amp;amp;nbsp; The book I have is 1997.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; He also goes into the best description I have read on IQ down conversion / up conversion and the math behind it.&lt;BR /&gt;
&amp;gt; &amp;amp;nbsp;&lt;BR /&gt;
&amp;gt; Jerry&lt;BR /&gt;
&lt;BR /&gt;</description>
      <pubDate>Tue, 20 Jun 2006 11:10:05 GMT</pubDate>
      <guid>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/380811#M190801</guid>
      <dc:creator>abhisheknag</dc:creator>
      <dc:date>2006-06-20T11:10:05Z</dc:date>
    </item>
    <item>
      <title>Re: FPGA - IQ</title>
      <link>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/381180#M191003</link>
      <description>Message continued here:&lt;BR /&gt;
&lt;BR /&gt;
http://forums.ni.com/ni/board/message?board.id=ifrio&amp;amp;message.id=91&lt;BR /&gt;
&lt;DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 20 Jun 2006 20:53:30 GMT</pubDate>
      <guid>https://ni.lithium.com/t5/LabVIEW/FPGA-IQ/m-p/381180#M191003</guid>
      <dc:creator>troy.perales</dc:creator>
      <dc:date>2006-06-20T20:53:30Z</dc:date>
    </item>
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