topic FPGA constant matrix times a vector using Linear Algebra Matrix Multiply in LabVIEW

FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

etgohomeok — Tue, 13 Aug 2024 17:22:39 GMT

Hi, I am attempting to use the Linear Algebra Matrix Multiply function in Labview 2013. I am attempting to multiply a 288x576 matrix by a 576x1 vector. The matrix is loaded from a file on the host computer and sent via a DMA FIFO to the target, and the vector is (for now) just filled with constants. In the future, the vector will be populated by data from an I/O module attached to the FPGA unit.

I am wondering if anyone knows about/has any experience with using the Linear Algebra Matrix Multiply function to multiply a constant 2D matrix by a vector.

I have attached a screenshot of my current attempt at a solution to this post. Because FPGA only supports 1D arrays, I have the matrix coming into my timed loop as a 1D array with a length of 288 * 576 = 165,888. I then take the first 576 elements using the Array Subset function and feed them into the Matrix Multiply function. The next iteration takes the second 576 elements, then the third, etc. Each of these sets corresponds to a row of my matrix, so I am effectively feeding the matrix in one row at a time, which is the type of input I have the Matrix Multiply function configured to accept (see the screenshot of the dialog attached).

The issue with my current solution is that the Array Subset function does not return a fixed-size array unless the "index" input is wired to a constant (https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/using-fixed-size-arrays-in-fpga-vis-fpga-module.html). For my application, the index at which I take the subset needs to change, and so the type of the wire coming out is labeled as "bounded size" instead of "fixed size." The code I attached a screenshot of performs as I would like it to when I run it on the development computer, however when attempting to compile to the FPGA I get an error about the small bit of wire (circled in the picture) that is "bounded size" instead of "fixed size."

If anyone knows any alternative methods to perform the type of matrix multiplication I described above, or a fix for the problem I am having with my code, it would be greatly appreciated.

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

MrQuestion — Thu, 15 May 2014 22:30:03 GMT

That is a lot of resources you will be eating up.

FYI: Last I looked you can't have a Quotient & Remainder Function inside a SCTL. Also, if each segment is 576 elements long, why are you using a quotient & Remainder function? Shouldn't you be multiplying by 288 instead?

Taking an array segment like this will not work because LabVIEW FPGA in it's current state isn't aware that the constant that you are feeding into the Array subset is a multiple of the fixed array size, and there are no checks to prevent the start location to be within bounds.

What happens when you want to take the 289th segment?

In regards to breaking up a complex array I have come across this issue before.

There are two ways (architecturally) to do this.

Both ways share a common technique.

Since you have a 1D array that essentially represents a 2D array, you need to have a mechanism to break up this large array into smaller 576 element chunks. You cannot do this with the Array Subset.

You have a choice to make for architecture.

1.) Have your array creation mechanism work in parallel with your Matrix Multiply, using parallel pipelining techniques, where you must have timing/syncing in place to ensure clean data out. (This is not for faint of heart, and suggest you don’t do this)

2.) Create a state type architecture (much easier)

In one state you will have a “Create Array”, and in the other you will have a “Multiply”

All arrays will be fixed size. In the “Create Array” state you will extract a single element from your “multiply” array and inject it into your defined array that is 576 elements long. After this array is filled you then transition to the “Multiply” state. You will then monitor the “Output Valid” boolean. Once this boolean is true you go back to the “Create Array” state. Repeat 288 times.

I hope that explains things. It might sound complex, but it isn’t really that hard.

I don’t have LabVIEW FPGA installed on my PC at the moment, or else I would show you a picture. If you need more help, I can make this on my home PC tonight.

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

GregSands — Fri, 16 May 2014 03:12:22 GMT

Have you looked at the Matrix*Vector VI which is in the Math/Control palette? It looks like a simpler way to do what you want, given that your Matrix is constant.

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

GregSands — Fri, 16 May 2014 03:25:31 GMT

Oops, just noted that the maximum array size for Matrix*Vector is 50x50. That won't work for you. 😞 Unless perhaps you can break both your Matrix and Vector up into 288x50 and 50x1 segments, and recombine the results after?

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

MrQuestion — Fri, 16 May 2014 14:03:16 GMT

Have you made any progress on this yet?

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

Dragis — Tue, 13 Aug 2024 17:24:37 GMT

Have you tried using the Row-wise or Column-wise element interfaces? Since the matrix is coming from the host one element at a time using the elemental interface will allow the Matrix Multiply to buffer things internally in the most efficient manner.

https://www.ni.com/docs/en-US/bundle/lvfpga-api-ref/page/vi-lib/rvi/linearalgebra/matrixmultiply/xnode/nifxpla-matrixmultiply-xnode.html

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

etgohomeok — Tue, 20 May 2014 16:14:25 GMT

Hi, I'm not sure as to how I would extract the single element from the multiply array if the array is being stored on the FPGA target. Would that not require the use of the Index Array or Array Subset functions, which return bounded-size or variable-size arrays unless the index input is a constant?

I'm also worried that switching between states in such an archecture would slow the processing. For this particular application, the large matrix will be a fixed constant for the duration of the program (it is a "calibration" matrix of sorts that is loaded from a file on the host computer's disk at the beginning of the program's execution and does not change until a new calibration is done). The 1D array that is being multiplied by it will be populated by data from a sensor. As such, I would ideally like to only create the calibration array once then stay in a state where I'm constantly reading data from my sensor and multiplying it by my calibration matrix. I believe that if the program is frequently switching to a new state that reads bits of the calibration matrix from the DMA FIFO, I wouldn't be able to achieve the rapid processing that I'm aiming for with the FPGA.

GregS, I was initially trying to use that particular VI, but as you said, it has the 50x50 limitation.

Dragis, I've looked into those interfaces rather than the Row Vector and Column Vector interfacs, however the latency jumps from ~1500 to over 300,000 clock cycles, which is too slow for this application.

I've considered the possibility of having 288 separate arrays and wiring them manually through switches so that I can cycle through them. Would that perhaps be the best (although also the most painful) solution that will retain the processing speed I'm hoping to achieve?

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

MrQuestion — Tue, 13 Aug 2024 17:25:08 GMT

When you replace array element in a fixed array the output is a fixed array.

If timing is a consideration you can always create a new clock, and do your Multiplication in a different time domain.

There are many ways to optimize designs depending on your needs. The linear algabra matrix that you are using is based off of fabric; and a lot of it, so you will probably hit an upper clock limit fairly fast. I'm kinda surprised that you aren't hitting clock timing violations already in a 40Mhz time domain.

Of course once you create the calibration matrix you wouldn't create it again. It would be stored in a shift register. You would never go back to that state again, unless you want to.

What type of FPGA are you using? There are many tricks to manage and manipulate large datasets in LabVIEW FPGA.

Depending on your FPGA you can really take advantage of the DSP48e Multiply and Accumulate function with a Dot Product algorithim. The DSP48e has no problems chunking away at data at a much higher clock speed.

Also, are you familer with the LabVIEW FPGA IP Builder? If you do take the split up in 288 separate array approach the FPGA IP Builder will save you alot of time.

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

dfjuggler — Mon, 11 Aug 2014 14:04:24 GMT

I'm attempting a similar thing. I wrote the following code which doesn't work as expected?

I was expecting this to work and I can't see why the first result is just repeated. I guess it has something to do with the hand-shaking, but I have no clue how to make it work.

Can someone help out? Thanks!

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

Matt_L — Tue, 12 Aug 2014 16:27:21 GMT

Hi dfjuggler,

So this part stood out to me:

Can you try just passing the array out? I don't think you should need to index. Also, since you're indexing at 0 each time, you're passing the same value into the new array.

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

dfjuggler — Wed, 13 Aug 2014 11:03:28 GMT

Thanks Matt, the thing is that the configuration I've set for the high-throughput matrix multiply VI outputs a 1D array of one element. The Index Array VI is basically there to turn the 1D array into a scalar. I was hoping that the first iteration of the For Loop would make the inner SCTL ouput the first result and so on with the second.

I've explored the process a bit more and realised I wasn't passing the second row of A at the right time. To illustrate the process I created arrays with the values for different signals part of the handshaking and got this result:

It seems that one needs to input the values for A and b during iterations 0 to 2. The results come 10 cycles later, at iterations 10 and 11. It should also be noted that during iterations 5 and 6, new values for A and b are being loaded, which means those will be used to provide results at 14 and 15. Similarly with values loaded on iterations 9 and 10.

I was intending to use this code as a SubVI, so I'm not sure it would work as is. It feels like I should be doing a cleverer management of the handshaking signals. For the time being, for this particular application I'll be using the Matrix*Vector block from the FPGA Math & Analysis >> Control palette. I've still got some studying to do regarding high-throughput VIs.

Thanks!

Re: FPGA constant matrix times a vector using Linear Algebra Matrix Multiply

MrQuestion — Tue, 13 Aug 2024 17:25:56 GMT

From experience I caution the use of SCTL within a subVI.

It is very possible that you will experience clock domain issues, and get compile errors.

Unless you intened to use some type of shared memory exchange, or FIFO where this is technically no longer a "subVI" but a parallel process. (FPGA's are good at this)

As soon as I get my home license going again I can create some sample code that will demonstrate the usage of the feedback nodes.

(I wonder when NI will get completly on the cloud bandwagon where I can just log onto NI and use the full version of LabVIEW.)

The "ready for A", and "ready for B" outputs are important feedback indicators.

Without feeding back these outputs in the next iteration there is no way of telling where you are in the processing pipe. If you know the configuration of the IP (such as how long the processing pipe will be) you might be able to get away without using feedback, but it is more complicated.

Also, the "output valid" output is is used to literally tell you when the output is valid.

Look at this Pipelining to Optimize FPGA

The matrix VI that you are using utilizes pipelining. As you can see from the diagrams on that page any data that you get out of this Matrix VI is junk unless this "output valid" is high.

-good luck