topic Re: I2S: Encoding and Decoding Signals in LabVIEW in Components

I2S: Encoding and Decoding Signals in LabVIEW

ninjaphil — Mon, 16 May 2016 14:38:43 GMT

Please provide feedback, comments, and questions on various I2S examples in this thread.

Generate / Acquire I2S Signals using High Speed Dogital I/O (HSDIO): https://decibel.ni.com/content/docs/DOC-47263

I2S Decoder using LV FPGA and RIO HW: https://decibel.ni.com/content/docs/DOC-1230

Re: I2S: Encoding and Decoding Signals in LabVIEW

KrisnaWisnu — Mon, 31 May 2010 07:20:55 GMT

Hi ninjaphil,

I am not familiar with the protocol, but just wondering if this reference design can be used with M Series Correlated DIO?

I would appreciate any advise.
Thanks.
Sincerely,

Krisna

Re: I2S: Encoding and Decoding Signals in LabVIEW

Hobbit13 — Mon, 27 May 2013 13:19:53 GMT

The NXP info link is dead, I2SBUS.pdf is no longer on their site.

Re: I2S: Encoding and Decoding Signals in LabVIEW

K C — Tue, 28 May 2013 06:42:41 GMT

Hi,

It's only 7 pages but it is a start.

Kees

Re: I2S: Encoding and Decoding Signals in LabVIEW

Patekkio — Fri, 26 Jul 2013 11:36:35 GMT

Hello

where can I download the vi's cited in http://www.ni.com/white-paper/9540/en (e.g. I2S_Decode_Formated_Data.viI2S_Decode_Formated_Data.vi) and also the physical connections to a DIO or FPGA board?

thanks in advance.

Giovanni

Re: I2S: Encoding and Decoding Signals in LabVIEW

Lennard.C — Wed, 20 Aug 2014 12:35:16 GMT

Hi,

I'm pretty new in this type of protocol. I'm trying to integrate the I2S to HSDIO. May I ask what is the connections I should make (I'm having HSDIO to generate and acquire at the same time without a DUT in between). How many bits does the I2S encode output uses?

Please advice

Thanks

Warmest regards,
Lennard.C

Re: I2S: Encoding and Decoding Signals in LabVIEW

Christian_L — Thu, 21 Aug 2014 17:29:08 GMT

In general I2S includes 3 signal lines. This I2S description should povide you most of the necessary information. I assume you will generate and read back the I2S bus, you will use 6 pins/channels in total, 3 out and 3 in.

https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf

Re: I2S: Encoding and Decoding Signals in LabVIEW

ASEAN — Mon, 25 Aug 2014 02:46:08 GMT

Hi Christian,

Thanks for the reply. I would like to ask if I were to use 4 channels in which consists of the Master Clock, Serial Clock, Word Select and Serial Data to the HSDIO, would it be possible to decode using the I2S decode portion from the example? If so, what are the changes (e.g. connections from the HSDIO or the code) I need to take note of? Can this I2S encode and decode subVIs can be used for general I2S encode and decode applications? What defines the value for "Master clock Over Sample Factor"?

I also noticed that there is a CLK IN/OUT function for the Master Clock however they are not enquiring external CLK in/out ports of the HSDIO.

Please advice

Thanks

Warmest regards,

Lennard.C

Re: I2S: Encoding and Decoding Signals in LabVIEW

Christian_L — Tue, 26 Aug 2014 18:34:09 GMT

Yes, If you have those four incoming signals you can pass them to the I2S_Decode function.

The array going into this VI must contain the combined data from the four signal lines in each element of the numeric array. i.e. each bit of the numeric value represents one digital line. Since you only have four digital lines the numeric values should be in the range of 0 -15. I have attahced an updated VI that shows the combined digital data and separate digital waveforms. Your data coming from the HSDIO should look similar to the combined digital data array.

The Master Clock Oversampling Factor represents the ratio between the Master Clock frequency and Serial Clock frequency. If they are the same it should be 1. In my example I used a factor of 4 so the MClk is four times faster than the serial clock. The serial clock corresponds to the updates of the Data line containing the analog values.

Re: I2S: Encoding and Decoding Signals in LabVIEW

nashm999 — Thu, 11 Sep 2014 14:31:54 GMT

Have you decoded and listened to any audio using this VI? I am just wondering what the quality of the data would be once it has been decoded and processed, any additional noise or distortion for example.

Thanks

Re: I2S: Encoding and Decoding Signals in LabVIEW

PrasanthTP — Mon, 16 May 2016 09:15:01 GMT

Dear all,

I need to decode data from Digital MEMS microphone (ICS-43432) using NI myRIO 1900.

I have attached below the screenshot of thte sytem block diagram of microphone.

In my circuit, I am using only one MEMS circuit and I have connected the

LR to 0 (GND)
WS to Connector A: Digital Input 0
SCK to Connector A: Digital Input 1
SD to Connector A: Digital Input 2

I understand that I can use FPGA in myRIO to establish I2S communication and tranfer the data from FPGA to RT Host using DMA FIFO

I have found your actual post from the link below

https://decibel.ni.com/content/docs/DOC-1230

When i tried to run this program in myRIO, i am neither getting any significant output nor I understand how the program works.

I suspect the program is running too fast when i obseved the iteration counter both in FPGA and in RT.

I am wondering how do i configure the loop speed to that of my preferred sampling rate.

I need to perform sampling, fs at a rate of 48 KHz.

From the data sheet of the microphone, i realised that

SCK = 64 x fs = 64 x 48 KHz = 3.072 MHz

It's also mentioned that it produes 24 bit data

Can anyone help me explain or understand how this I2C program shown below works.

If not, can you provide me with some reference links.

Thanks in advance

FPGA screenshot

Real Time Target Screenshot

Re: I2S: Encoding and Decoding Signals in LabVIEW

Christian_L — Thu, 19 May 2016 21:53:41 GMT

I'll try to give you some help on this example.

The Read Loop, which is the blue structure is a Single Cycle Loop and runs at the clock rate of the FPGA, which is 40 MHz by default.
The Read Loop synchronizes itself to the I2S signal by looking for the edges on the SClk and WS (LRClk in the FPGA code), so you do not need to configure the loop speed. Based on these edges and the number of bits, the read loop uses a simple state machine (implemented using the various case structures) to read the SD line, collect the data bits in a register, and transfer the collected data using the DMA FIFO.
After starting the FPGA VI the Read loop sits in the Wait for Start case. After starting the read operation from the Host VI, the Read loop goes into the the Synch Start case.
In the Synch Start case, the FPGA is reading the WS (LRCLk) line looking for a falling edge, which indicates the start of the Left Channel, and goes into the Read state.
In the Read state, the FPGA VI looks for rising edges on the SCLk, which is the indicator to read the SD (SData) line. On the next cycle of the read loop it reads the SD line and writes the bit to the Sample Value register.
The Bit Counter register keeps track of how many bits have been written to the Sampe Value register. After the configured number of bits have been collected, the Sample Value is written to the DMA FIFO.
While looking at the SClk, the FPGA VI is also looking for the WS (LRClk) signal to change, which indicates the end of the current channel and beginning of the next channel. At this point the Bit Counter is reset and the VI is starting to collect the bits for the other channel.

Looking at the datasheet for your microphone, the sensor outputs 24 bits per channel, but skips the first sample. Therefore you need to set the number of bits per sample to 25. After acquiring 25 bits from the SD line, you will have the 24 bits of valid data in the Sample Value register for transfer to the RT host VI. In the host VI, you should mask the data to the 24 bits to remove the extra bit acquired. This can be easily done using the Boolean And function (see example).