PLL circuit with 3 IC's

[aruwin]

Please tell me in detail which wire should go to which number (eg. A1, B2, C4 etc...). 

I am in need of big help here. I don't know what else should be done to get this correct. 
I have to build this PLL circuit and choose any 3 N (integer) of the N-divider. Then I have to observe the input signal Sig_in and the output signal VCO_out for each N. The result should be that the output frequency is N+1 times bigger than that of the frequency set by ELVIS (function generator), if I have understood the instructions correctly. I attached my results. The output signal looks weird, right? When I set N as 1, the output signal gets messed up 😕 I tried for N= 4 and 8, the waveform looked just the same as when N=1. What should I do? By the way, where should I connect the 5th pin of IC 85 (A=B) to? In the diagram it just shows a short line not connecting to anything. 

I took 4 pictures of different angles so you can see better.   

http://www.flickr.com/photos/98820721@N04/11870437296/sizes/o/in/photostream/

http://www.flickr.com/photos/98820721@N04/11870033074/sizes/h/in/photostream/

http://www.flickr.com/photos/98820721@N04/11870445586/sizes/k/in/photostream/

http://www.flickr.com/photos/98820721@N04/11869882813/sizes/k/in/photostream/

[johnsold]

aruwin,

1.  Please attach your images (.png or .jpg, no bitmap) directly to the post. The little tree icon in the toolbar at the top of the post text box allows you to insert images.  Many people on the Forums do not like to go to third party sites to veiw images for security reasons.

2. I do not see any images of your signals. You show images of your circuit, but not the results.

3. The values of C, R1, and R2 will give your VCO a center frequency in the tens of kilohertz range. This will not allow locking to harmonics of a 4 MHz clock.  I got this information from page 5 of the Fairchild datasheet for the device.

4. The maximum frequency of the HC4046 VCO is 12 MHz (at minimum Vcc = 4.5 V).  Thus, the circuit should not be expected to work for any N > 2.

5. The A=B output of the compartor is not used and may be left unconnected. Also, all the unused inputs on the other half of the HC393 should be grounded. Unused inputs can cause strange things to happen in CMOS ICs.

I suggest trying to get this working at frequencies in the tens of kHz range first and them moving to higher frequencies of needed. Your breadboard may have excessive stray impedances and lack suitable bypassing to work well at tens of MHz.

Lynn

[aruwin]

Thanks for the reply. I forgot to attach my results, sorry. Here they are:

[johnsold]

Please keep everything in this thread.  No one is going to try to debug the photos of your wiring shown in the other thread.

Do you understand how the 4046 works? When you have both R1 and R2 connected you have a limited range of frequencies from the VCO. Page 5 of the Fairchild datasheet for the 74HC4046 shows fmax/fmin no larger than 7.5 to 9.5 regardless of the ratio of R2/R1, depending on the value of Vcc. For R2 = R1 fmax/fmin ~ 1.7.  So the circuit you have cannot possibly work for more than one value of N!   Well, maybe it would work for a few closely spaced values at the high end of the range.

Study the datasheets. Decide what specifications you actually want to meet. Calculate the minimum and maximum frequencies at the VCO output. See if you can select values for the VCO and filter passive components which might work. Then try it.

Also, look at the logic design. I doubt it does what you expect. Try drawing a timing diagram manually and look at the A>B and A<B outputs.

When you are troubleshooting a PLL circuit, it is useful to look at the output of the phase detector or filter. That will tell you if it is trying to force the VCO to one extreme or the other. It will also tell you whether the signal is steady, oscillating periodically, or moving somewhat randomly. Each of those can be a clue as to what is going on. Also look at the A>B and A<B outputs of the comparator.

Lynn

[aruwin]

How to check the maximum and minimum frequency of VCO?

[johnsold]

Read the datasheets.

Lynn

[aruwin]

Where is the datasheets?

By the way, is this ok?

[johnsold]

You can find datasheets for the ICs by an on-line search. You may also have databookks with the information in your labs or in the library.

I cannot tell what you are asking in the photograph.  Please ask the question with respect to a schematic diagram.

Lynn

[aruwin]

Build this circuit and choose any 3 values of N of the N divider. Observe the input signal Sig_in and the output signal vco_out for each N. Make sure that the output frquency is equals to "frequency from ELVIS x (N+1)" even if the waves are not completely locked.

This is exactly what the instruction says.

This is what I have done:

[SteveD123]

You've sent me a private message asking for help with this problem.

As this is a school exercise, here are the debugging steps I suggest:

1. Aquire the datasheets for each of the ICs in the circuit.
2. Decide where to open the loop to be able to measure the open loop transfer function. I leave deciding where to open the loop and what kind of signal to inject as a learning exercise.
3. Check that each part of the open loop circuit behaves as you expect. Any errors in wiring should become clear during this step.
4. Conduct a PLL loop analysis of the closed loop system. "The Art of Electronics" Book by Paul Horowitz and Winfield Hill contains guidance.