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This note explains how to use external VHDL code that makes use of Xilinx core components through a CLIP.
It is an extension of the NI documentation covering CLIP/IP integration.
LabVIEW already includes a Xilinx IP integration palette, which wraps the Xilinx Core Generator features pretty well. However, you may want to integrate some more complex code relying on Xilinx core IP components, which you obtained from a third party or which you wrote yourself with another program. Obviously, you don't want to rewrite the whole code in LabVIEW.
I explain here what must be considered to integrate your code as a CLIP. To demonstrate my purpose, I created an instance of an Adder-Subtracter from the Xilinx Core Generator. If you installed the the LabVIEW FPGA Module Xilinx Tools, you will find it installed on your computer. Mine was in c:\NIFPGA\programs\Xilinx14_7\ISE\bin\nt64, but this will of course depend on your version of LabVIEW and your install path:
When including some Xilinx core components within a project, there are two files you should keep an eye on:
1) the VHDL wrapper, with extension .vhd
2) the Core Generator log file, with extension .xco
Integration in a LabVIEW project
As in the aforementioned white paper, in the Project window, right-click on the FPGA target and select Properties.
Go to the Component-Level IP sub-topic and click Create File.
Select now the necessary VHDL files and the XCO files associated with the Xilinx core components:
The XCO contains all the customization parameters of the core component, including the FPGA target model. In the next page, you must therefore specify this:
Carry on from this point as explained in the NI white paper.
Optional: set the clock source for your CLIP correctly
In many Xilinx Core configuration modules, it is necessary to mention at what clock rate the component will be driven. Don't forget to set the clock source of your CLIP accordingly. To do this, go to the CLIP properties:
Core components with memory initialization files (MIF)
Some components, such as the FIR Compiler, require some pre-computed data to be stored. The core generator produces a MIF, which is required during compilation. The VHDL file generated by default requires that the MIF sits in the same folder as itself. Remember therefore to add it to the synthesis files along with the required VHD and XCO files. While checking syntax, LabVIEW will copy these files to a temporary folder and try to compile. Check for the cannot open 'filepointer' errors, which indicate that one file mentioned in the VHD script is missing.
