6602 Save Registers and FIFO

[Dr_DeV]

Hello,

I've been searching through the forums and noticed that their are many oppinions concerning the size of the onboard memory buffer for the PCI-6602 board.  Some say the board has a 1 or 2 sample buffer (FIFO) while others say the board has a 16 sample FIFO.  I was hoping someone could clear this up for me.

Lets assume that we are running a buffered event counting measurement using DMA transfers.  What I understand from the register level programming manual is that the counter has two save registers (Gi HW, and Gi SW).  When a gate signal latches the counters count, it places it into one of these registers.  The next count would be placed into the second save register.  My understanding is that the DMA transfer, sends the data in the save registers directly to the internal buffer configured by the user on the computer running the DAQ software.  This would mean that the save registers on the card are the FIFO buffer that everyone talks about, and thus the card only has a 2 sample buffers because each counter only has 2 save registers which each hold only one 32bit number.  Is this correct?

If it is not, then what happens?  If it is correct, then where did this idea of a 16 sample FIFO buffer come from?

Thank you for your help,

Matt

[nayer]

Hello Matt,

You are correct each counter has 2 sample FIFO and here is the data flow.

Counter register -> 2 Sample FIFO on 6602 -> Transferred across PCI Bus using DMA -> RAM Buffer -> Read by software

I did see the forum post which says about 16 FIFO for a TIO board, but could not find any documentation on that. Apart from that here is the knowledgebasethat talks about the buffer size of 660x boards. 

Thanks

nAyer