CTR1_GATE pin defaults to output?

[PotatoPhysics]

My goal is to count pulses connected to CTR1_SOURCE using the Frequency Measurement VI. I've noticed that when I connect the CTR0_OUT to CTR_GATE the CTR0_OUT goes high but the VI indicates a timeout condition. I believe this to mean that counter 1 did not see a trigger on its gate input which is strange because I certainly did.

I discovered in the manual for the PCI-MIO-E series that all of the pins such as PFIx/CTR1_GATE are all configured as outputs be default. God only knows why one would want the counter gate to default to to output pin. I have no idea how to instruct the CTR1_GATE pin to become an input connected internally to the counter's gate. I'm running Labview 5.1 and I don't have access to all the fancy CVI function ca
lls that reconfigure the signal routing. There are the AO* and AI* VI's but those only work on triggering analog stuff. There is no mention of ay other VI's being capable of fiddling with the routing.

Does anyone know how I can make the gate and source pins become inputs?

[bman]

Where in the manual do you see the Gate is configured as an output? It is actually configured as an input only. For the Measure Frequency VI, if you are using counter 0, connect the OUT of counter 1 to the GATE of counter 0 and the signal you are measuring to the SOURCE of counter 0.

What this is doing is, counter 1 is generating a pulse with a known width, 2 seconds for example. Counter 0 is simply counting pulses from the unknown signal for the duration of those 2 seconds.

Brian

[PotatoPhysics]

Page 4-41, PCI E Series Service Manual
Quote:
"Any PFI pin can externally input the GPCTR0_GATE signal, which is available as an output on the PFI9/GPCTR0_GATE pin... You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge... As an output, the GPCTR0_GATE signal reflects the actual gate signal connected to general-purpose counter 0. This is true even if the gate is being externally generated by another PFI. This output is set to tri-state at startup. "

This pin is certainly NOT input only. It may be tri-stated by default. I wish I knew how to select a PFI pin to be the GPCTR0_GATE from LabView.

I know how this frequency counter thing is supposed to work-it just doesn'
t. There isn't enough documentation on how to control the routing inside these boards from LV.