Generating two synchrouns digital clocks with python nidaqmx

[manuru]

I am trying to generate two synchronous clock for sensor control (i2s protocol shown in the figure below). The main clock (CK) is at 1024hKz. The other one (WS) is 1024/64hKz but should be changing polarity on the negative edge of the main clock.

I am trying to address it by using counters with Python. here is my code:

cltask = nidaqmx.Task(new_task_name="clki2s")

clk_i2s = "PXI1Slot2/ctr0" #PFI12
clk_ws = "PXI1Slot2/ctr1"#PFI13

frequency_clk_i2s = float(1024000) # 16kHz * 64
frequency_ws_i2s = float(frequency_clk_i2s/64)

delay_ws_i2s = (1/frequency_clk_i2s) / 2


cltask.co_channels.add_co_pulse_chan_freq(
   clk_i2s,
   #name_to_assign_to_channel="",
   units=FrequencyUnits.HZ,
   idle_state=Level.LOW,
   initial_delay=0.0,
   freq=frequency_clk_i2s,
   duty_cycle=0.5
)
cltask.co_channels.add_co_pulse_chan_freq(
   clk_ws,
   # name_to_assign_to_channel="",
   units=FrequencyUnits.HZ,
   idle_state=Level.LOW,
   initial_delay=delay_ws_i2s,
   freq=frequency_ws_i2s,
   duty_cycle=0.5
)
cltask.timing.cfg_implicit_timing(sample_mode=AcquisitionType.CONTINUOUS)

Even  using the delay (delay_ws_i2s) the output are two not-syncronized clocks (I guess there is some initial random jitter somewhere). i.e. WS does NOT change polarity on the negedge.

Do you have any suggestion for this problem? Or potential alternatives?

[Kevin_Price]

I'm no help with the Python syntax, but what you need is almost certainly possible with a pair of counters.

1. Configure Ctr A as your CLK signal.  Don't start it (yet).

2. Configure Ctr B for pulse generation with units of "Ticks".   Set High Ticks, Low Ticks, and probably also Initial Delay to 32.  So low for 32 cycles of A then high for 32, making a divide-by-64 overall.

3. Configure Ctr B to use Ctr A output as its timebase, falling edge polarity.

4. Start Ctr B.  Nothing will happen yet as you haven't started up the timebase signal, Ctr A.

5. Start Ctr A.

6. Ta-Da!

-Kevin P