How do I fix the offset between counters in my buffered event counting?

[Briconn]

Hi

I'm working with the pci-6602 card and 2 avalanche photodiodes (APDs).  The goal is record the events in 1ms time intervals so that value 1 in first row of the array (counter A) corresponds to value 1 in the second row (counter B).  I have the counters in an array and the program operates using the ni-tio sub-vis obtained from the buffered event counting vi found from the example code library.  Basically the counters are read into the buffer past a gate and the frequency is controlled by a pulse train.  The data is then read out from the buffer into an array which is displayed and plotted.  One problem I'm having is that when I test the program with a function generator being counted in both counters the number of events per bin (1ms) are not always equal.  I get the same number of total counts 2000 (2sec) but the arrays seam to have a slight delay sometimes.  That is column 5 row 1 may be 20 and column 5 row 2 may be 23.  I've verified on an oscilliscope that the two functions are synchronized and overlapped.  My guess is that there is some millisec delay in the program when it fills the buffer.  Is there any way to define the readout precedure to account for this so that it will readout row A from when it was first input to when it was output and then readout B from when B was input to when it was output? 

-Brian Connolly

[Kevin_Price]

It sounds to me like you need to configure both the counting tasks to be hardware-triggered, and generate that trigger after you've started both tasks.  This will cause their measurements to start at the same t=0 time.

With counter measurements under DAQmx, I think you'll need to use the DAQmx Trigger property node to set up an "Arm Start" trigger.  I've often configured it to use PFI0 which also happens to be DIO0, aka port0/line0.  Then I can simply toggle that bit True & back to False to generate the needed synchronizing trigger.

1. Configure and start a DIO task for Dev#/port0/line0.  Write the bit False.  (Your hw may default low anyway, but this makes sure). 

2. Now configure the two counting tasks for triggered start off PFI0 and start them.  They are ready but not counting yet because they need a trigger.

3. Write the DIO bit True and then False.  This will cause the 2 counting tasks to start with their t=0 times in sync.  You can now clear the DIO task.

4. Be sure to read = #'s of samples from both counter tasks so you stay in sync.

Good luck!

-Kevin P.

[Briconn]

Well, I haven't tried to use a trigger yet.  I was going over the program with a more experienced user and we noticed that the pulse train generation sub vi uses traditional daqs but my program uses ni-tio daqs.  I'm not sure this is the cause offset.  I should explain the offset better.  It looks like sometimes their is a blip in the counter.  At first I thought it was electronic but the functions look fine on the scope.  Using 4000 Hz function and 1000 Hz aquisition time the counter should count 4 each column.  so it should look like 4 8 12 ...  but instead and always at the beggining there will be something like 4 11 15 ... also sometimes there is a down blip so it would be like 4 11 15 18...  The position of these blips fluctuates but is always close to the start. 

Maybe there is a difference way to generate the pulse train that is more compatible with the ni-tio daqs that I'm using?

[Tom_W_[DE]]

Hi Briconn-

Are you using a counter to generate a sample clock for a buffered event counting operation?  It sounds like this is the method you really need- basically a way to make sure that readings taken from the count register always correspond to a known position in time.  I would strongly second Kevin's suggestion to use an NI-DAQmx example such as "Count Digital Events-Buffered-Continuous-Ext Clk.vi" (and "Gen Dig Pulse Train-Continuous-Dig Start.vi" to generate a triggered pulse train). 

If you must use Traditional NI-DAQ (Legacy), this example would be a good starting point.

Hopefully this helps-