09-21-2005 03:58 AM
09-21-2005 07:33 AM
Ralph,
Briefly, no. When you generate a finite pulsetrain, the driver uses 2 counters. One is set to generate output while its gate input (pause trigger input) is high. The other helper counter is used to generate a single precisely-timed pulse that allows the 1st counter's pulses to be output for just the right amount of time needed for the correct finite # of pulses.
Can any of these work-arounds help? You could generate continuous pulsetrains with both counters and then stop them under software timing. If you've got LV 7.1, you can use the pulses as a timing source for a timed loop for better timing reliability. And if you're really stuck, there may be a convoluted way to use 5 V analog outputs as though they were the single pulses...
-Kevin P.