Counter/Timer

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NI FPGA

Hello everyone, am designing a basic counter on the NI FPGA platform to work on the Basys3 FPGA board. I did the design schematic on the Multisim PLD design and when I simulate it works fine. However, when I transfer the same circuit to the FPGA it does not work. Am trying to have the seven segment-display on the FPGA board to display the count number. Any advice on how I can achieve this?

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Hi Bhowizx,

 

Can you give us more information on what are the steps you are taking to pass the design from Multisim to the FPGA. Also, in which hardware is the FPGA being used?

 

Warm Regards,

Enhernan

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