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PCI6602 output, sink mode

Can a PCI6602 be set into a "sinking output" mode?

 

If so, what are the highest levels of voltage and current the PCI6602 can pull down when generating a 500Hz PWM? Are the outputs isolated?

 

Idealy, it would be great to see a schematic if the 6602's output circuit.

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Hey gholt,

Are you using a counter or digital output to generate your signal? If you are using a digital output you can change the Digital Output Drive Type.

The outputs are not isolated on the 6602. Current specs are listed in the 6602 specifications manual below. I have also attached some other useful resources.

NI 660x Specifications
https://www.ni.com/docs/en-US/bundle/ni-660x-specs/resource/372141b.pdf

What is Sinking and Sourcing?
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019LBbSAM&l=en-US

How Do I Connect Two Sinking I/O or Two Sourcing I/O Together?
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000YI7ICAW&l=en-US

Regards,

Chris Delvizis
National Instruments
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Hello Chris,

 

While my PCI-6602 puts out a 5V PWM signal, I have noticed that NI avoids mention of a 5V output capability in the specs for the card. They simply say "TTL/CMOS, with a minimum "on" of 2.4V".

 

Is it safe to assume that the PCI-6602 will be able to produce a 5V PWM signal at one counter output, with a sink/source capability up to 4mA? (Other counter pins will be used as inputs in my application.)

 

 

 

 

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gholt,

 

When the specs for the 6602 list the output capability as TTL, they refer to the established standard that "logic low" will be between 0 - 0.8V and "logic high" will be between 2.2 - 5V.  The specifications for the PCI-6602 that Chris linked list a maximum input current of 200 µA for the digital input lines.  The counters on a board will always accept the same or most likely less current that the digital lines.

 

This board cannot sink a current of 4 mA.

Seth B.
Principal Test Engineer | National Instruments
Certified LabVIEW Architect
Certified TestStand Architect
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Hello Seth,

 

The specs for the digital logic levels read "Output low voltage (Iout=4mA)" and "Output high voltage (Iout=4mA)". What is the meaning of the "(Iout=4mA)"?

 

Also - Is there anywhere I can get some definate specs on the counter outputs? I'm starting to think I will need to design a buffer circuit to convert PWM signals coming out of the PCI-6602 into an open drain type output. 

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I've done some research on my end, because the information listed in the data sheet is inconsistent with the information in the specifications manual.  The data sheet information is incorrect.  This is likely because the data sheet is a marketing document that has passed through several hands for simplification, and on occasion information is incorrectly interpreted.  We are currently working to institute a new method that will allow for marketing documentation to simplify intricate R&D specifications in an easy-to-read yet still correct format.  I apologize for any confusion this may have caused.  For now, the best policy is to always rely on the product manual and the specification manual for the most accurate information.  You can access this documentation from the product page by selecting Resources » Manuals.

 

According to the specifications manual for the 6602, when the digital output line is being driven to the "logic low" state of 0.4V or less the current is "24 mV" and at logic high, the current is "-13 mA".  With respects to our digital level specs, positive current flows into the board and negative current flows out.  Thus, at "logic low" the board can sink 24 mA and at "logic high" it can supply up to 13 mA.  Please note, however, that at "logic high" the board has a very minimal sinking capability.  If the board has to sink anything beyond an extremely small current in the "logic high" state, the board will be damaged.  Likewise, at "logic low", the board cannot supply current.

 

I hope this clarifies the issue.  I'm sorry again for the inaccuracy in our data sheet.  The specifications manual should have the information you need.

 

Seth B.
Principal Test Engineer | National Instruments
Certified LabVIEW Architect
Certified TestStand Architect
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