PCIe-6321 counter failing at high frequency

[saratoga]

I'm trying to use the counter on the 6321 as a frequency divider that takes an 80 MHz sin wave input and generates a 10 MHz square wave output by digitizing the output of a 50 ohm device on PFI0.  The specifications to for my board list a counter "Max Source Frequency" of 100 MHz, leading me to believe that 80 MHz should be possible.  However, in my experimenting while the counter based divider works very well at lower frequencies, it fails at about 35 MHz by missing edges.  The result is an  unstable output frequency that bounces between 8:1 division, 9:1, 10:1... depending on how many  edges are missed.

To explore this problem further, I swapped out my 2 meter 68-pin VHDCI for a 1 meter and plugged my function generator into the break out board with a < 30 cm cable, thinking that perhaps impedance mismatch was an issue.  However, even with < 1.5 m,  the device still works at 30 MHz and fails at 35 MHz.  This suggests to me that impedance mismatch is not the problem, as the maximum frequency was unchanged even though the cable length was nearly halved.   

Is there something else I'm missing?  Is there a faster interface than PFI?  Or someway to 50 ohm terminate the device? 

[johnsold]

The counters on most DAQ devices expect digital signals, not sine waves.  Input high voltage (Vih) 2.2 V min, 5.25 V max.  Input low voltage (Vil) 0 V min, 0.8 V max.  I have the specs for the 6341 and they do not specify a minimum rise and fall time but many counters and digital inputs are not happy with rise and fall times greater than ~10 ns.

If you want to count sine waves, place a fast comparator between the sine gnereator and the counter.

Lynn

[John_P1]

The max source frequency is 100 MHz, but this is referring to the internal 100 MHz timebase which may be routed to the counter.

The "external base clock frequency" (strange way to word it, I know) is only up to 25 MHz according to the specifications.  The protection circuit on the external PFI lines won't allow for frequencies much greater than this.

Best Regards,

[saratoga]

Are you  100% certain?  The website makes no such mention of that limitation:

https://www.ni.com/en-us/shop/model/pcie-6321.html

And in fact that page would be extraordinarily misleading if in fact limited to 20 MHz.  In that case though, is there a NI product that I can use? 

[John_P1]

I see what you mean, but I guarantee you can't pass a 100 MHz signal through the X Series PFI lines.  ~25 MHz is what the bandwidth of the protection circuit is specified for (it's mentioned in this KB for instance).  I'm not sure offhand about the RTSI lines though (it might be worth an experiment as the bandwidth doesn't seem to be specified anywhere, but I wouldn't be too optimistic).

As for other NI hardware, the 6602 can take an external source up to 80 MHz on its PFI lines assuming the input signal is a clean square wave at TTL voltage levels (I've actually pushed this up to 100 MHz in the past, but your results may vary).  It is programmed in DAQmx like the 6321.

Or you could just implement this with an external circuit (e.g. comparator + ICS542).

Best Regards,

[saratoga]

Thats unfortunate.  I was hoping for a ready made solution so that I don't have to prototype a board since I don't have much experience with RF design.  I was thinking of buying one of thse:

http://www.pulseresearchlab.com/products/freqdiv/prl-220_240/220A-240Amain.htm

To divide 80MHz down to 20 MHz and then feed it into my X series board, but I'm a little concerned about how accurate that would be.  For this application I need to have extremely good phase locking between two clocks.  Any missed edge would result in data corruption.  The 6602 would also be an option, but again I'm wary of operating near the limits of what the device can handle.  

I'm curious what you'd recommend?

[johnsold]

The devices you linked from Pulse Research Lab also have logic inputs - not sinusoidal inputs.

Digital dividers are very accurate, provided that you supply them with clean input signals.

What is the source of the 80 MHz sine wave? What is the amplitude? Does the frequency, phase, or amplitude vary? How much noise is present?

Many years ago I worked on a phase locking system that was very sensitive to transients, so I may be able to help if you fillin som eod the details.

Lynn

[saratoga]

I spoke with PRL about it, and they said a sin input will likely generate a little more cycle to cycle jitter due to lower slew rate, but this isn't a series problem for me.  I don't mind if individual edges are off by a few hundred picoseconds, so long as I can accurately count (and then divide) the total number.  Analogy:  I want a gear that won't slip, but a bit of vibration is tolerable.  Will probably just put an amp to gain the signal a little and increase the slew rate.

The actual source is a photodiode on a pulsed mode locked laser.  The output is ultrastable in both amplitude and frequency.  I'm filtering it down to extract the fudimental as the duty cycle is very low and I wasn't sure about detecting very high bandwidth delta-like pulses with a slow counter.  I can also play around with the LPF cutoff and see if including the 160 MHz 1st harmonic helps the slew rate much.  

I ordered one of those dividers and will try it out in a couple days.  Also grabbed a cheap ebay frequency synthesizer that used a 125 MHz oscillator.  Going to see if I can knock it off and use it as a cheap divider.  I'm still interested in better solutions, but if the PRL device does allow me to lock a NI board to my laser without dropping cycles, that'd be pretty good.

[johnsold]

I saw on their website that PRL also has some comparators which will take sine signals as small as 10 mV and generate TTL or ECL level outputs. One of those might be the place to start.

Filters will introduce phase shifts.  At a fixed frequency the shift will be constant, but if phase is important you may need to compensate.

The most robust way of dealing with low duty cycle signals is to use a comparator to produce a logic level pulse and follow that with a pulse stretcher circuit. The pulse stretcher is often a monostable multivibrator but can also be implemented with high speed synchronous logic.

Filtering a low duty cycle signal may result in a very low amplitude output.

Lynn