Before this thread gets too old and dusty, I'm gonna post the example I worked up. The descriptions I give are from memory b/c I don't have a LV pc nearby and it's been a week or so since I last opened it. If there's any response here, I'll follow up with more description and comments.
Keypoints:
1. Generates a finite pulsetrain with an exact # of steps by using features built into the counter hw. The minimum # of steps is 2. The counter configuration is pretty much as described earlier in this thread.
2. Allows the pulsetrain to have its frequency varied on-the-fly. This is useful for ramping a stepper.
3. The frequency update operates in a timed loop that uses the pulsetrain as its timing source. This guarantees that we don't get the error from changing a freq setting 2 times before the first setting produces a full pulse cycle.
4. Another counter from the 660x is used to count edges of the finite pulsetrain and give hw verification of the # of pulses generated. (If you remove the code involving this counter, I think you should be able to use the example with an E-series or M-series board too).
5. The ramping algorithm is pretty crude, but the intent is to produce a ramp where the frequency changes linearly with time (not with step #). On each iteration of the timed loop, I calculate the appropriate delta freq based on the current frequency and the time since the last freq update. In a real app, this algorithm would need further work including a means for ramping down.
Happy counting!
-Kevin P.
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