Retriggerable buffered counting edge task

[Admitry]

Hi,

I am performing buffered noncumulative TTL pulses counting using NI6602 board. Basically, what I am doing is performing period measurement on Ctr0 (Configured as CIPeriodChan) using an external stable periodical signal (1MHz) connected to Ctr0Gate and a signal to measure connected to Ctr0Source. Therefore, each time when a rising edge arrives to Ctr0Gate, the counter buffers its current value, resets the count register back to zero and keeps counting until next pulse arrives to Ctr0Gate. As a result I get the number of counts registered within a Gate signal period. Ctr0 and paired Ctr1 are using 80MHz internal timebase source.

My questions are:

1. How much time does it take to register a rising edge arriving to the CtrnGate?

2. How much time does it take to "latch" the current counter value, start transferring data using DMA, reset the counter value to zero and be ready count new pulses upon registering edge on Ctr0Gate?

Specification says that the maximum frequency the counter is able to resolve is 80MHz. But is that true when performing buffered counting?

Basically, the question is what is the 'dead time' between two buffered measurements, when the counter skips incoming pulses?

Thank you,

Admitry

[Kevin_Price]

Speaking as a long-time user of NI counters, but without deep knowledge of the circuitry, signal propagation times, and suchlike, here's a shot at answers plus some further comments.

1. In my understanding (and have never read otherwise) this is very fast, pretty much driven by propagation time through the logic circuitry.  Probably a small # of nanosec.

2. Latching, resetting to 0, and being ready to count new pulses is also very fast, as above.  The sticking point you'll run into is the transfer via DMA.

The 6602 has a 2-sample FIFO it uses to buffer count values for DMA transfer.  If you think that isn't very big, well, you're exactly correct.  It's a major factor limiting the acquisition rate of the 6602.  Several newer boards have beefed up the FIFO for counters and as a result can handle much higher sustained acquisition rates.  

From various threads here, the upper limit for the 6602 seems to be in the low 100's of kHz for sustained acquisition.  Here's one such thread where I linked to further performance benchmarking info.

A newer 6612 or an X-series board would very likely support the 1 MHz acq rate you want, but the 6602 will probably throw errors related to FIFO overrun very early in the task.

Sometimes counter tasks can be approached inside-out where you exchange the role of the source and gate, and perhaps do a little post-processing on the data.  One that keeps coming up here is photon detector measurements.  Measuring intervals of individual APD pulses has often resulted in the task error I referred to (especially on older boards like the 6602).  Many people settled for "binning", where they configured the APD pulses as a counting source and used a lower constant rate clock for the sample clock (gate).  Instead of measuring every detected photon period, they measured # of photons per regular interval.  Both result in photons/sec, the tradeoff is accepting the averaging of the latter method in return for a measurement that doesn't error out.

-Kevin P

[Admitry]

Hi Kevin,

Thank you for your reply.

1 & 2 are indeed pretty much what I see. I performed test buffered counting of the 12.5MHz source sugnal with the sampling rate of 1MHz and did not see any single lost count. So at least with these frequences I can be safe. 

Right as you mentioned my photon counting task is approached inside-out and I measure the # of photons per 1 us. I have to say though, that I have never seen an overwrite error at my 1MHz sampling frequency (2MHz is too fast, though). Usually I acquire 1-2 MS. So that 100 kHz you mentioned might depend on the certain application, I guess.

Thank you again,

-Admitry

[Kevin_Price]

I wouldn't have counted on success at 1 MHz, but because the rate has always been known to be "system dependent", it's not shocking that you're able to achieve speeds a few times faster than the info reported previously on the site.  A lot of the 6602 benchmarks are probably several years old now, leaving room for some speed improvements in the systems that use them.

Glad you're able to achieve the 1 MHz target rate without need to change hardware.  Just keep in mind the option that newer hardware handles high speed counter acquisition more reliably due to the larger FIFO (and perhaps also the PCI-express bus).  If you run into issues down the road or start needing faster acq rates, it'd be a pretty seamless upgrade.   The 6612 looks like the most direct replacement for a 6602, but an X-series MIO board would be an overall better option for many people due to its flexibility.

-Kevin P