Start and Stop of a Digital Pulse (DAQmx example)

[CV]

I have a question. I'm using a PCI 6110 card and I'm generating a pulse train, using the VI GenDigPulseTrain-ContinuousPauseTrigger (DAQmx).
Everything works fine. But I would like to generate a pulse train that starts when a ttl pulse arrives on pfi9 for example, and stops when a pulse arrives on pfi8 (or any other input channel) using the DAQmx driver instead of the traditional daq. Is this possible? I've tried to modify the forementioned VI but I did not manage to do that.
Thanks in advance for any help.
-Claudio

[Kevin_Price]

Since the question has been sitting a couple days, I'll take a shot for you. Just don't consider this to be a 100% rock-solid answer.

You're proposing a concept of a start and stop trigger that are wired to physically different pins. That sort of concept is supported for analog input, but I can't think of a way to support it for pulse trains with the 2 counters your board has. The best I've come up with would require 3 counters and an external logical AND gate.
In case other hardware is available (or perhaps you can budget for a PCI-6601), here's an outline of the concept:

1. Two counters are configured for retriggerable pulse generation, with extremely long (duration of experiment) pulse widths and short delays. They will be of opposite polarity.

2. The "start trigger" causes counter A to fire a looooong high pulse after a minimal delay. (Its output will be low until the start trigger arrives.)

3. The "stop trigger" causes counter B to fire a loooong low pulse after a minimal delay. (Its output will be high until the stop trigger arrives)

4. Counter C will generate the desired pulse train with "pause triggering" set up to allow pulses when the logical AND of (output A) & (output B) is high,
suppressing them when the output is low.

Notes:
A. If the "stop trigger" arrives before the "start trigger," you're hosed.
B. There's a tradeoff between the duration of the two looong pulses and the timing resolution required by them. The durations can be about 53, 214, or 42900 sec for resolutions of 12.5, 50, and 10000 nanosec respectively.
C. If you use a 6601, you can generate an intermediate frequency between 100 kHz and 20 MHz as the timebase to give you more options for the tradeoff listed above.


Alternative with more external circuitry:
If you can do a little more logic circuitry, you can probably replace the functions of counters A & B above with a circuit, and require only one counter on the board you've already purchased.
Replace counters A & B with two one-shots of looong duration, and invert one of them. AND them together, and feed the result to counter C's pause trigger input.

-Kevin P.

[Tiptop]

Hello,


While Kevin has a great suggestion, I think that you could get this to work with two counters, and two logic gates.

Here is what I propose.

1.) Counter 0 is set to simple event counting with a counter of 16777214, so it will toggle it�s output state with one more pulse and then toggle again with another pulse. This way you can logically or your stop and start triggers together and wire the output on this one line. The output will be used to gate your continuous pulse generation.


2.) Then you can logically and your output signal from counter 0 with your pause trigger signal, and wire that as your pause trigger for your continuous pulse generation. The total effect should be a continuous pulse train that has a start, stop and pause trigger
.

Let me know what you think, or if I was unclear.

Best regards,

Justin T.

[CV]

Hi justin,
thanks a lot for your reply. I will try your suggestion in the next days. It seems very reasonable.
Thanks again for all your help.
-Claudio

[CV]

HI kevin
thanks for your suggestion. Even from the one of justin.
Thanks too for suggesting the 6601. In fact I'm short on counters on my daq and it was a good suggestion. Considering how cheap the card is I've in fact ordered one yesterday after reading your message.
thanks a lot
-Claudio

[Kevin_Price]

So Counter 0 is setup to "pulse on terminal count", making the output state toggle on two consecutive source edges. By presetting the count value to be one cycle prior to the pulse, the toggles will occur on the first two source edges, no matter how far they happen to be separated in time. That's a pretty cool idea!

In step (2), do you really need to logically AND the counter 0 output with anything? It seems to me that it would already behave like a "pause trigger" all by itself.

Also another note to the original poster: this 2-counter solution has some "failure modes" just as my 3-counter solution did. It will start on the first pulse from either the start or stop signal, and will also stop on the second pulse from either
one. This could potentially be an issue, depending on your setup. Is there any guarantee that your experiment will always produce the sequence start-stop, and never start-start, stop-stop, or stop-start?

I think you could probably substitute some type of flip-flop for the OR gate in Justin's step (1) to eliminate such sensitivity to trigger sequence. Exactly which type I'm afraid I can't say off the top of my head. You'd have to check datasheets for something that produces a constant low output until the first "start trigger" signal edge, then will leave it high until a subsequent "stop trigger" signal edge. I guess you'd also need the output to then remain low despite any subsequent "start triggers." Hmmm, maybe you need something else paired with the flip-flop...

Anyone?

-Kevin P.

[Tiptop]

Hey Kevin,

In step (2), I was assuming that the user might want to have a pause trigger as well as a start and stop trigger. It was my assumption that Claudio wanted to keep this functionality. If not, you could possibly remove all external gates. You could set up a gated continuous pulse train with a digital start trigger, and use the same toggle counter just to apply a gate which would end the output. Then in software, realize the end has been reached because of the change in count, and end both counter operations. This would also help out with trigger order, as an end trigger would always end the operation, and extra stop triggers would be fixed because the software is checking the count (There would be a delay time from software checke
d where the pulse train could be turned back on by too many stop triggers). Also, extra start triggers would be ignored.

So Claudio,

If you want to have a start, stop and pause, then the first solution that I posted would work, but Kevin is right, you may need some more circuitry if there could be bad scenarios.

If you do not need the pause trigger, you could remove all external circuitry and just use two counters.

Let me know what you all think, or if there is a better way.

Best regards,

Justin T.
National Instruments

[CV]

hi justin and kevin
well I'm always astonished on how useful this newsgroup is and how quick to have a comments from members of the community.
In fact I need just a start and stop. Usually there is no mistake in the experiment I'm doing about when the start and the stop are coming. Actually they coincide with the beginnig and the end of the experiment. I do not need the pause so I'll go ahead as you and kevin suggested.
Thanks for all you help.
Best regards
-Claudio

[Kevin_Price]

Very nice solution! I'm still getting up to speed with DAQmx -- I take it the ability to generate a pulse train that's triggered *and* gated is a new capability for E-series boards under DAQmx? Am I right in thinking that under traditional NI-DAQ, one would have to choose between a retriggerable single pulse *or* a level-gated continuous pulse train? Or else use a 6601/6602 board?

Anyhow, thanks for hashing this stuff out -- I'm glad to have learned a neat new trick.

-Kevin P.

[CV]

Hi justin and kevin.
After reading your comments I've tried to play with the Terminal Counter (I never knew it existed).
I've just readjusted one of the example vi of labview and tried to test the condition TC reached, to stop a counting loop on a counter.
It seems that using a 6110 and a 100KHz input frequency (the one to be counted) the counter stops not right after having reached the TC, but a little bit later. Do you have any suggestion on how to solve this problem? The counter by default is counting on a 20 MHz timebase, correct?

Thanks
-Claudio