beginner stuff: cRIO digital frequency measurement

[Jeff MHRT]

Thanks again for the replies, I've been taking a break lately for obvious reasons, but I'm back into it now.  I've played around with a loop timer in a flat sequence as you suggested and it seems to work pretty well.  I looked at typical examples of counters using SCTLs and was able to implement the same ideas in a flat sequence, with shift registers in the While Loop that encompasses the flat sequence.  Thanks a lot for your help, and enjoy the rest of the holidays.

Jeff

[Jeff MHRT]

So just to follow up, here's a screenshot of the counter I set up using a flat sequence with a loop timer.  So far it seems to be working as I expected in the little bit of testing I've done with it, but I was just hoping to get confirmation that what I'm doing isn't fundamentally wrong in one way or another, as I haven't seen anything exactly like this in any examples.

On top of this, I've got a Host VI that takes in the period through a Read/Write Control, takes the reciprocal for frequency, and then stores this in an array alongside the digital signal and a tick count, and writes this to a spread sheet.  I'm just starting to learn how to do this stuff, sorting out sample rates and the like, but right now I just want to make sure my FPGA VI is sound.  Thanks for your input!

Jeff 

[StephenB]

Looks good to me! Glad to see things are going well for you.

Have you considered upgrading to LabVIEW 8.6? In 8.6 you can use Scan Mode, meaning you can use the inputs and outputs of the C series modules on your cRIO without having to program the details of the FPGA, and one of the features is built in counter FPGA code. You also get better DMA FIFOs, FXP support, and more functions fit in the SCTL.

Also, block diagram clean up is nice 🙂

[Jeff MHRT]

Hi Stephen, thanks for the assurance.  I'm working on University licensed software, and the whole school seems to be on 8.5 right now.  Ever since I've started working on this, I keep seeing references to 8.6, and I've generally gotten the idea that it would be a lot easier to work with, and thanks for touching on some of the details on why it's so much better.  I'm not sure what will be involved in getting an upgrade, at least for our little project which has some kind sponsorship from NI backing it, but I'll see if I can start pulling some strings, wherever those strings may be....  Built in counter FPGA code sounds very nice!

[Jeff MHRT]

Hi Stephen, I finally managed to get LV 8.6, turns out it was already at my school gathering dust.  Just installed it yesterday, and I've been taking a look around.  I was going over the "Getting Started with the cRIO" manual to check out Scan Mode.  I'm just building a system at home without any hardware attached, and I've noticed that under Scan Interface mode, a module like 9401 can actually configure it's various channels as counters.  This would be very attractive to us (we're doing data aq on a hybrid race car, we'll eventually have 4 wheel rpms, and 3 motor rpms to monitor) but if I'm not mistaken, only the FPGA chassis with 3M gates can support Scan Mode, while I have a 9102 Chassis.  So, unless I'm mistaken (please correct me if I'm wrong!) I can't run in Scan Interface mode, and therefore I wouldn't be able to configure DI ports as counters.

If that's the case, anybody wanna trade Chassis???   

[Robbob]

If I could jump in this thread...there IS a workaround to the 3M gate limitation of scan mode.  By default, the scan mode engine that runs on the FPGA and allows the scan engine to run is larger than 1 million gates.  However, if you build a blank FPGA VI and compile it, it will rebuild the engine to fit on a one million gate with only support for the modules currently inserted and detected.  This VI will take a long time to compile (~30 mins on a decent computer) since it is trying to do a lot of optimization, but once it does, you will be able to run scan mode.  You will need to initially set your cRIO in scan mode, and then click on chassis and add an FPGA target.

On the other hand, there is no rule saying you can't code FPGA and build your counters manually, it isn't horribly difficult.  FPGA is much more flexible than scan mode, and there is nothing scan mode can do that FPGA cannot since the scan mode engine is built on the FPGA in the first place.  Then again, you will get started much faster using Scan Mode, and you wont need to continuously compile every time you make a change(minus the initial blank compile you did to allow your scan mode to run on 1M gates)

Let me know if you need clarification on any of this~

[sharda]

I am interested in doing a similar hing with the 9403 with 9014-controller. I was interested in having a quick look at the program. can you please post 2 or 3 screen shots of FPGA and host VIs.

I will appreciate.

Thanks,

Ajay

shardaj@auburn.edu

[sharda]

Hi Rob,

I have quick question, I am using 9403 to measure frequency, I am clear about the time period and counting the rising edges, but I want the count of the rising edges to reset after each sampling or completion of the sequence structure. I am using a while loop and a sequence structure to get thing done. Can you please help me out.

Thanks,

Ajay 

[Robbob]

Are you using the Scan Engine or FPGA programming?

FPGA: Use a simple case structure to reset your counter.

Scan Engine: How Do I Reset a Counter When I am Using CompactRIO Scan Mode?