cRIO: FPGA loop running at twice the onboard clock speed

[CucchioDaQuanchi]

Hello,

I have a pulse counting application using the NI cRIO 9053, which currently uses the onboard clock for timing (40 MHz):

This works basically fine, but I am missing 80% of the pulses because they are coming in at a too high rate. (pulse width is ~10 ns)

I thought about using a faster loop speed, by creating a "derived clock" at 80MHz:

I've been modifying the FPGA VI accordingly:

but that doesn't work at all.

I guess I have been a bit too naive here and I am now assuming that I will need a (much more expensive) PXI system if I want to catch all the pulses.

I would be grateful for any advice or confirmation of my suspects.

Best,

Alex