inverting and outputing a finite pulse train

[Sneakytiki]

I am using a PCI-6602 card and labview to generate 4 digital finite pulse trains (2MHz to 6MHz range) to be sent to a amplifiing circuit that will drive transducers.  I have a VI based on a finite pulse train sample VI I found, but the driver requires both the signal, and the inverted version of the signal.  I tired using XOR gates to do this before, but because of rise and fall times, the signals end up overlapping a slight bit, which causes a short between +V and -V supplied to the amplifier.  Is there a easy way to have Labview invert my signals while having no overlap?  I have access to another PCI-6602 if needed.

I tagged a jpeg of what my VI looks like at the bottom.  Any help in this matter would be much appreciated.

 Thanks

[Doug_L._Bear]

You could write out the same signals to the 4 more lines and invert the logic on those lines using a channel property node»digital output»invert lines.