resource is reserved error when configuring 2 retriggerable pulse trains on PCI-6602

[kirkm]

I'm getting the following error when I try to start the 2nd of two retriggerable pulse trains:

NON-FATAL RUN-TIME ERROR

HallTestDAQ.c line 1574, col 18 thread id 0x0000044C
Function DAQmxStartTask: (return value == -50103 (0xffff3c49)
NI Platform Services: the specified resource is reserved. The
Operation could not be completed as specified.
Task Name: _unnamedTask<1>

Status Code: -50103

Any idea what is going wrong??

Here's a snippet of  the code that sets up the counters:

  // *************** COUNTER 0 ****************************
  DAQmxCreateTask( "",&cthCounter0PulseGeneration );
 
  DAQmxCreateCOPulseChanTime (cthCounter0PulseGeneration, pci6602DevPlusChan( "ctr0" ), "", DAQmx_Val_Seconds, DAQmx_Val_Low, 0.005, 0.01, 0.01 );

  DAQmxCfgDigEdgeStartTrig ( cthCounter0PulseGeneration, "/Dev1/PFI0", DAQmx_Val_Rising );

  DAQmxCfgImplicitTiming (cthCounter0PulseGeneration, DAQmx_Val_FiniteSamps, 5);

  DAQmxSetTrigAttribute (cthCounter0PulseGeneration, DAQmx_StartTrig_Retriggerable, TRUE);

 
  // ********************* COUNTER 1 **********************************
  DAQmxCreateTask( "",&cthCounter1PulseGeneration );
 
  DAQmxCreateCOPulseChanTime (cthCounter1PulseGeneration, pci6602DevPlusChan( "ctr1" ), "", DAQmx_Val_Seconds, DAQmx_Val_Low, 0.005, 0.01, 0.01 );

  DAQmxCfgDigEdgeStartTrig ( cthCounter1PulseGeneration, "/Dev1/PFI1", DAQmx_Val_Rising );

  DAQmxCfgImplicitTiming (cthCounter1PulseGeneration, DAQmx_Val_FiniteSamps, 5);

  DAQmxSetTrigAttribute (cthCounter1PulseGeneration, DAQmx_StartTrig_Retriggerable, TRUE);

Thanks,

Kirk

[Brad_K]

Hi Kirk,

Finite acquisitions and generations on TIO devices actually use two counters behind the scenes. The second, "paired" counter is selected automatically based on the first: ctr0 uses ctr1 (and vice versa), ctr2 uses ctr3, etc. Change your second channel to a counter that isn't paired with the first, such as ctr2.

Brad

[kirkm]

Brad, thanks for the help on this.

OK that makes sense.

Here's a followup question.  Where is this fact documented for the PCI-6602?

I thought I had read everything I could find.  I even downloaded the latest user's manual which seemed to have less info than an older one I have from some time ago.

Any pointers on where to find additional docs will be much appreciated.

Thanks again,

Kirk

[Brad_K]

Hi Kirk,

That's strange, I would expect the NI 660x User Manual to explain how the different counter applications work. I'll file a corrective action request about the NI 660x User Manual, but in the meantime I'd recommend referring to the M Series User Manual, which explains why finite pulse train generation uses two counters on page 7-22.

Brad

[Brad_K]

Also, there is a mention of finite pulse train generation in the paired counters page of the NI-DAQmx Help, but the explanation in the M Series Manual is better. And I misspoke regarding finite acquisitions: buffered finite acquisitions (event counting, two edge separation, etc.) do not use the paired counter.

Brad

[kirkm]

Now that I know I'm looking for info on paired counters I went back and checked again in my old 6602 user's manual.

In the paragraph titled "Finite Pulse-Train Generation" it does say "Two counters are used for this application"

It's on page 3-17 of the manual dated January 1999, Part Number 322137B-01.

Kirk