two counters, large range frequency measurement in fpga

[hr_martin]

Hello NI-community,

I'm trying to implement the "Measure Time of Known Number of Cycles" in FPGA (for explanation see http://www.ni.com/white-paper/3619/en#toc3 ). I'm using the NI cRIO-9074 chassis and a 9401 DI/O module. The signal to measure is in a range of 1000 to 10000 Hz. I expect to get the most accurate results from the methode mentioned with two counters. 

I just found some usefull hints for doing this with a DAQ device. (https://decibel.ni.com/content/docs/DOC-11542 ).

How do I code the first counter? Am I right to look for ex. an rising edge, count n (= divisor) zero crossings switching the signal to pos during this period (= logic-high of the divided down signal), repeating that for the low-level and forward it to counter 2?

I would be very thankfull for some help.

Regards

Martin

[Aurelie]

Hi,

have you already read this ? http://forums.ni.com/t5/Counter-Timer/9401-counter-issues/m-p/2143278

Aurelie

[Aurelie]

oh sorry, I read it a little too fast... have you already had a look at the example for measuring frequencies in LV FPGA ? (Toolkits and Modules -> FPGA -> FPGA fundamentals -> Fixed Count - cRIO) (and it supports an NI 9074). An implementation of the first counter is there to be seen in the single cycle timed loop. You can also notice that you are right you look for the rising edge that you obtain by detecting when the signal goes from False to True. 

Aurelie