Clocking on rising and falling edge of req.

[Fluxengr]

I'm not sure why my 6534 is clocking on the rising and falling edge of my in coming clock. If you use one of the examples from Labview for DIO, such as pattern IO. How can you tell what state the program is clocking on? Is there anyway of forcing a rising edge reaction to the incoming clock on the req line?
Thanks

[Marni]

Hello Fluxengr. Thank you for contacting National Instruments. You can specify the state on which the program is clocking in the active edge input of DAQmx Timing.vi. If you are using Traditional DAQ with pattern I/O, the REQ polarity is active low, which means data is either latched or output on the falling edge of the clock. (http://digital.ni.com/public.nsf/websearch/2FB93421FAD8374286256BDF007A78AF?OpenDocument) Please let me know if you have any questions. Have a great day!

Marni S.
National Instruments

[Fluxengr]

Thanks Marni