Digital Buffer Write misses one of two buffer iterations

[Torero]

Hi, I have written a program where group 1(output)is defined as Port A and B and group 2 (input) as Port C and D on the PCI-6534. One line of group 1 is connected to REQ2 and another to ACK2 on group 2. Even though there are enough REQ pulses for group 2 (input) to collect its data, the "buffer iterations" on the Digital Buffer Write is always the double amount of the "number read" on Digital Buffer Read. Since The input part of the program is not retriggerable it always start over and over again whilst the output part of the program is on a controlled output loop(Dig Buffer Read and Write under the same Case Sequence that is always true). On the other hand running the Buffer Output Loop VI will always show a "bu
ffer iteration" that steps up by one and not by two. What is wrong with my program?

/Torero

[John N]

Hello,
I have a few points to mention that might help.
First, REQ2 and ACK2 are not both going to be inputs, so it sounds like something is fundamentally not quite right about the design you are using.

There are some examples that have documentation and should help you to figure out a good method of doing what you want to do. They are in LabVIEW\examples\daq\digital\653x.lib

Depending on the mode you want to use, you can find different examples there.

For the double size buffer you are getting, I am not sure what you are using to determine that you are getting twice as much data. Since the arrays of digital data are always 8-bit, a two port input will be two entries in an 8-bit array. This could look like a double-sized array if it is interpreted as single
8-bit values instead of paired 8-bit values.

Hope this helps. If you look through all of that and need more, please send more information about your design so that I can understand what might be going wrong.

Regards,
John N
Applications Engineer
National Instruments

[Torero]

Hi again! Thanks for the answer but I've already based my program on thoose examples. This time I also provide some images showing a schematic of the setup and another of the program diagram. I would like the "buffer iterations" and the "numeric IN" numerics to step up equally if I know that I am reading less or exactly the same data that the circuit is providing. Nevertheless buffer iterations outratios "numeric IN" by 2:1 when the program is running. When I tested the Buffered Pattern Looping Output alone it was just stepping up with one, but now when I combined both Buffered Pattern Looping Output.vi and Buffered Pattern Input Trig.Vi the behaviour is different. Since the PCI-6534 is not retriggerable I let Group 2 to start again when the aquisition is r
eady. Perhaps an alternative way is to have a Continous Buffered Pattern Input-Trig.Vi with the trigger sent out only in the beginning? Unfortunately I haven't found such an example in the VI-Examples.