Digital Output on both rising and falling edge of internal clock

[JackStaff]

Hola,

I am using a PCIe-6537 device and LabView 8.6. This device has an internal clock of up to 50 Mhz. I am trying to output a digital square wave at the maximum rate of 50MHz. I set my clock rate to 50MHz, build my array of 1's and 0's, convert it and output the digital waveform (on port0/line0 if it makes a difference). When reading the wave on a scope it shows a [pretty] good square wave, but of only 25 MHz. The reason I believe is because the DAQ card is only output one sample (1 or 0) for every rising edge of the clock, and not the falling. Therefore the output wave will always be twice as slow as the clock rate. Is there a way to output on both the rising and falling edge of the sample clock so that I may achieve a 50MHz square wave, or should I try a different technique?

I'm all ears...

~JS

[Raajit_Lall · Accepted solution]

JS,

The capability of generating/acquiring on both the rising and falling edge of a clock is called double data rate (DDR).  We have an app note on using DDR with our instruments.

Advanced Features of Digital Devices: Double Data Rate

The board that you are using however, is not capable of double data rate.  The only devices capable of DDR right now are the NI 6561 and the NI 6562, which are LVDS boards.  You can output on the rising edge or the falling edge not both.  You could use external circuitry to generate a 50 Mbps signal.  Basically, you would need an XOR gate and combine two different channels to create a 50 Mbps signal on a 50 MHz clock rate. 

Here is an example of how you can achieve this.  The white paper that I mentioned above walks you through this process.

 

On the other hand, we do have 100 MHz boards which will give you a 50 MHz square wave, like the one you are looking for.  The NI 6542, 6552, 6544 and 6545 are all 100MHz or greater.  The PXIe-6545 is a 200 MHz board.  You could use one of those boards to generate higher frequency signals.

Hope that helps.  Let me know what your thoughts are on that. 

[JackStaff]

Raajit,

Thank you for your response. It was very informative! Here's is what I've learned. 

According to the link,  the boards capable of DDR are for low speed applications because your can still only operate at half the speed of the internal clock. However being able to trigger on both rising and falling edges can be very useful for some applications. But I need it trigger on consectuive rising and falling signals so that option is out. Figure 1 shows that the DDR data changes on both rising and falling edge of the DDR clock, which is half the speed of the sample clock. 

Using an xor gate to logically create the 50MHz signal is a great option. It can be used to create a simple square wave or a random square wave, and the NI recommended semiconductor can operate at speeds well beyond what I require. The problem I forsee here is the boards maximum sampling rate. The 6537 has a 200Mb/s throughput. This means that if I we operating at 50 MHz that I could only switch 4 channels at a time and each xor gate configuration requires 2 channels, limiting me to producing only 2 signals. My question is then, if to adjacent channels are switching on a rising and falling edge respectively, it would be fine when both were logic low or either one was high, but not when both are high? 

The third option to get a new card seems the most efficient and simple, but with the cards starting at $7k, it is not the most cost effective. 

For my application, I am trying to achieve at least one ramp square wave, operating at the clock rate, and two random square waves. Any way to get 3 signals from 4 channels?

Thanks again for all the information! 

JS

[Keith.Shapiro]

Hi!

The 6537 actually has a 200MB (megaBYTE) per second throughput, not 200Mb (megaBIT) per second.  The 6537 can operate all 32 channels at 50MHz.

Hope that helps,

Keith Shapiro

National Instruments R&D

[DJ_L.]

Hey JS,

So if you just need a clock at 50 MHz, then you can actually use the Export Signal function/VI to output the 6537's onboard clock to the PFI4 line. For your other square waves, you can use the data lines to output them at rates based off of the 50 MHz clock, so like 25 MHz like you saw and others that will be 50 MHz/N (this is of course if you need 50% duty cycle square waves). Hope this also helps.

Regards,

DJ L.

"For my application, I am trying to achieve at least one ramp square wave, operating at the clock rate, and two random square waves. Any way to get 3 signals from 4 channels?"

Message Edited by DJ L. on 06-25-2009 04:57 PM