Errors introduced using ConfigureSampleClock

[broke]

Thanks for finding out my error in requesting the DELAY attributes D.J.  

I have not had much time to work on this, but I have made 2 changes to my code and it will now intermittently pass (every 1 out of 3 trials or so...)  The two changes I have made:

1) I changed my SystemTimingSettingsUpload function to set all the pins to SAMPLE_CLOCK_RISING_EDGE immediately after changing the clock frequency, and then immediately set the pins that I want delayed to their delay values:

    def SystemTimingSettingsUpload(self, DRC_freq, Gen1_del, Gen2_del, Gen3_del, Acq1_del, Acq2_del) :
        """Updates HSDIO system frequency and digital timing settings based on passed values"""

        self.SYS_DDC_freq = 2.0 * DRC_freq

        DLL_Sync.niSync_SetAttributeViReal64(self.SYS_Sync_session, self.NI_VI_NULL, self.NI_NISYNC_ATTR_DDS_FREQ, c_double(self.SYS_DDC_freq))
        DLL_DIO.niHSDIO_ConfigureSampleClock(self.SYS_DIO1_gen_session, c_char_p('PXI_STAR'), c_double(self.SYS_DDC_freq))
        DLL_DIO.niHSDIO_ConfigureSampleClock(self.SYS_DIO2_gen_session, c_char_p('PXI_STAR'), c_double(self.SYS_DDC_freq))
        DLL_DIO.niHSDIO_ConfigureSampleClock(self.SYS_DIO3_gen_session, c_char_p('PXI_STAR'), c_double(self.SYS_DDC_freq))
        DLL_DIO.niHSDIO_ConfigureSampleClock(self.SYS_DIO1_acq_session, c_char_p('PXI_STAR'), c_double(self.SYS_DDC_freq))
        DLL_DIO.niHSDIO_ConfigureSampleClock(self.SYS_DIO2_acq_session, c_char_p('PXI_STAR'), c_double(self.SYS_DDC_freq))
        
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO1_gen_session, c_char_p('0-19'), self.NI_NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO2_gen_session, c_char_p('0-19'), self.NI_NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO3_gen_session, c_char_p('0-19'), self.NI_NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO1_acq_session, c_char_p('0-19'), self.NI_NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO2_acq_session, c_char_p('0-19'), self.NI_NIHSDIO_VAL_SAMPLE_CLOCK_RISING_EDGE)

        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO1_gen_session, c_char_p('0'), self.NI_NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPositionDelay(self.SYS_DIO1_gen_session, c_char_p('0'), c_double(Gen1_del))
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO2_gen_session, c_char_p('0,1'), self.NI_NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPositionDelay(self.SYS_DIO2_gen_session, c_char_p('0,1'), c_double(Gen2_del))
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO3_gen_session, c_char_p('0-18'), self.NI_NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPositionDelay(self.SYS_DIO3_gen_session, c_char_p('0-18'), c_double(Gen3_del))
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO1_acq_session, c_char_p('1-14,19'), self.NI_NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPositionDelay(self.SYS_DIO1_acq_session, c_char_p('1-14,19'), c_double(Acq1_del))
        DLL_DIO.niHSDIO_ConfigureDataPosition(self.SYS_DIO2_acq_session, c_char_p('0-19'), self.NI_NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE)
        DLL_DIO.niHSDIO_ConfigureDataPositionDelay(self.SYS_DIO2_acq_session, c_char_p('0-19'), c_double(Acq2_del))

 2) The second thing that I changed is I reload the Vih/Vil/Voh/Vol settings for all cards immediately after calling the timing settings changes.

Now that it is intermittently passing, I'm going to take a closer look at the captured records when it fails to see if I can see any patterns.  I think I do, but I need more time to study it.

I would say you shouldn't spend any more time on my issue until I take more time on my side to evaluate the most recent results and write some more code to download attributes to check the status of the cards.  I'll write a function to debug out lots of attributes and then call it before and after calling my timing function.  I'll report back tomorrow hopefully.

Thank you,

Brian

[broke · Accepted solution]

Doh!  Seems kind of obvious now that I found it...  

I had to add 1 line to my "SystemTimingSettingsUpload" function to solve my problem:

    DLL_TClk.niTClk_Synchronize(c_ulong(3), self.SYS_DIO_session_arr, c_double(0))

I was calling niTClk_Initiate to start the generation sessions, but after changing the clock frequency I was not calling niTClk_Synchronize again to re-synch the generation sessions.  (I previously only had 1 "Synchronize" statement in my whole program, right after initializing the cards and setting them all to the standard test frequency...   I never used to issue a "Synchronize" again.  The test operators could test thousands of parts for hours and hours without my code ever calling Synchronize again.  Of course, I was never changing the DDC rate either, but I'm thinking that was maybe a bad idea to not periodically force the generation sessions to re-synch?

It feels like I need more training in the proper use of niTClk, niSynch, and niHSDIO for multiple card dynamic generation and acquisition applications.  Can you point me to the best white paper or example code that I should review for best practices?

Thanks,

Brian