How to do a frequency locked loop using labview

[Keith Tan]

Hi there, I dont know whether this is the right board to post this thread.

But in any case, I have a external frequency which I would like to keep it at a certain value, for example 10Mhz. But due to noise, etc to the circuit, I keep getting ranging from 9.80Mhz to 10.20Mhz.

I know i will need to use something like a phase locked loop system, in this case, frequency locked loop system. For the output of my PXI-6552, I will need to produce relevant voltages so as to fine tune it to 10Mhz consistantly.

Are there other ways in labview which I can do this? Or rather, how can i create a frequency locked loop using labview

Thanks alot for your assistance and help. 

[Jesse_O]

Keith Tan,

THe PXI-6552 has a PLL (phase lock loop), and is capable of using an external reference clock to increase the accuracy of the output frequency.  If you are using a PXI based product (and from your post you are), then you also have the option of using the PXI backplane clock as your reference.  

To set the reference source there is a VI under the HSDIO palette in LabVIEW (under Configuration >> Adv Timing) called niHSDIO Configure Ref Clock.vi.  Using this VI you can set the reference source to PXI Clock.  Alternatively you can take a look at the example in NI Example Finder called Dynamic Generation with Reference Clock (PXI).vi.  You can find this VI by selecting Help >> Find Examples and navigating to Hardware Input and Output >> Modular Instruments >> NI-HSDIO >> Dynamic Generation >> Non-Scripted.

Regards 

[Ryan_M]

Keith, I had briefly mentioned in your previous postings that implenting a software defined PLL loop for an external oscillator will not give you good phase noise performance. Since you loop is totally dependent on software, your response will be slow (relative to a hardware implementation) and may not be deteministic. With the right loop dynamics, you shoud be able to track low frequency drift to the accuracy of your HSDIO clock but you wont be able to filter out any sort of higher frequency perturbatons. You can model your PLL's loop response and try and design some proessing that helps but you're going to need to get deeper into loop design, which LabVIEW can certainly help you with. In your previous thread you mentoned that you're usin an HSDIO device to capture an ADC waveform from and oscillator with an HSDIO, use LabVIEW to grab an FFT then use the HSDIO to drive a digita pattern to a DAC to tune the oscillator. If you need better determinisim, I might look at a RIO based approach. The 7831, for exampl, has integrated ADC and DAC channels. Then you can use LabVIEW FPGA to progrm a deterministic loop in hardware.