I am trying to perform pattern generation with an external clock using a 653X board. I did not have a true understanding of the handshaking options, and erroneously set the handshake source option to the default "I/O Connector" value. I also set the following handshaking modes: Signal Mode (Edge), Edge Mode (Leading), REQ Polarity (Active High), and ACK Polarity (Active High). I think I was essentially generating an ACK pulse for every REQ pulse that I was receiving. I completely ignored the ACK pulse and assumed my data was getting clocked in via the REQ pulse. What I observed was a loss of my MSB bit and an added bit (always zero) at the LSB end. So when expecting 1
1001 I was acquiring 10010. It was as if the bits shifted left and stuck like that for the rest of the acquisition. I realize I was running in the incorrect mode by performing handshaking when I should have been performing pattern generation. Regardless, what was occuring in the handshaking mode that produced this shifting of bits and holding at those values for the rest of the test. I need to understand what was happening so I can properly explain the differences between handshaking and pattern generation modes, as well as, explain the cause of this bad data. My application was running properly most of the time, even though I had set the incorrect mode. Only on rare occasions was bad data acquired which caused this shifting of bits occuring. All inquiries are greatly appreciated and thanks for the help.
