Limitation in number of DMA FIFOs for multip-up parallel comm with FPGA

[ethen99]

Hi

I am using 7820R in a project to send data back and forth between host and target. So far ,my setup was 4 and in target I have 4 SPI engines that they can run fully in parallel

They all had their own DIO for SPI and their own DMA FIFO for read and write . I have 4 DMA write and 4 DMA read to send data between host/target. Now I want to expand this code to 16UP

I don't have any limitation in number of DIOs but now I need 16 FIFO read and 16 FIFO write and 7820R only has 16 FIFOs

Is there any design that I can just use 1 FIFO for read/ 1 FIFO for write and I can still keep the fully parallel model so the SPI engines can run fully in parallel?

[Terry_ALE]

Can you interleave the data? This can help save on FIFOs.

[ethen99]

I can interleave the data , but on top I have multiple sequencers that async can call DMA FIFOs . Since there is a dedicated FIFO right now there is no problem

But if I use 1 DMA FIFO then I have to make the execution  of that FIFO serially   - non reentrant and that means I will lose  parallelism  

[santo_13]

If you need true parallelism, you're limited by the number of available FIFOs. On the other hand, you can create pseudo-parallelism by creating an aggregator on the host side, which will asynchronously gather data from all sources and serialize them to the FPGA and vice versa. This way, all your clients would not be bogged down by a non-reentrant API.

This is how even most instrument drivers work, whenever there can be more than one session with the same hardware.

[Terry_ALE]

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@ethen99 wrote:

I can interleave the data , but on top I have multiple sequencers that async can call DMA FIFOs . Since there is a dedicated FIFO right now there is no problem

But if I use 1 DMA FIFO then I have to make the execution  of that FIFO serially   - non reentrant and that means I will lose  parallelism  

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The 7820 allows for multiple samples per cycle on DMA-FIFOs.  The total depends on the datatype.  If you go to the DMA-FIFO's properties under Interfaces, you will see the option "Number of Elements to Read" (or Write).  In this case you can 'widen' the DMA-FIFO so you can send more than 1 element.  This will allow you to maintain the parallelism/throughput that you had with 4 DMA-FIFOs.