Must an external PCLK signal be maintained during burst mode?

[CAS]

I am using a PCI-DIO-32HS card to read in 2 byte data using an external clock connected to PCLK. I am using burst mode and have found that I need a FIFO between my peripheral device and the PCI-DIO-32HS as otherwise I lose data whenever the half-buffer is transferred.

The original FIFO design stopped the PCLK and data transfer when the ACK line was deactivated by the PCI-DIO-32HS. This did not work but experimenting has led us to believe that the clock signal must be continued for the ACK line to ever become active again. Is this correct - i.e. the PCLK signal must be maintained and only the data transfer paused while the ACK line is inactive?

The manual does not appear to give this amount of detai
l about the requirements but timing diagrams and some of the words could possibly be interpretted as suggesting that PCLK is required at all times.

[SachaE]

Hi,
PCLK must be a free-running clock. This means that if using an internal PCLK, the PCLK signal starts before the actual transfer begins, and may last beyond the end of the data transfer.

You are using an external clock. This means that if you want to transfer N samples, you cannot just give the PCLK line N pulses. PCLK must be running for a few cycles before and after the data transfer. Unfortunately, this makes it very difficult to use the PCLK to transfer a precise number of points. We have observed that the PCI-DIO-32HS board needs about 4 clock periods before and about 3 clock periods after the transfer. However, these numbers are not true constants and may vary from one transfer to the next.
A better approach would be to externally de-assert t
he REQ line when you no longer wish to transfer data.

Hope that helps

Sacha Emery
National Instruments (UK)

[CAS]

Thanks Sacha.

The device producing the original clock signal in our system is a free-running clock - that's no problem. The instrument is continuously outputting data and we wish to acquire a few seconds of the data at certain times.

It is actually the PCI-DIO-32HS card which is stopping the transfer by deasserting the ACK line. It is at this point that our FIFO was pausing the signal to the PCLK input while it waited for the ACK line to be reset. We now have a working system in which the FIFO continues the clock signal at all times but only transfers data when the ACK line is set.

Does the requirement you mention for pulses before and after a transfer also apply to these periods when my system is trying to input data but the card has deasserted the
ACK line?

CAS

[SachaE]

Hi,
Not 100% sure. I cannot find anything concrete on this, but I would say it's the first thing to check if you find you're losing data when the 32HS card returns you the ACK signal again. The free running clock should means that you will be OK when the ACK is de-asserted. It's the start and end of the whole process that's affected.

Sacha Emery
National Instruments (UK)