07-05-2016 12:10 PM - edited 07-05-2016 12:15 PM
Hello,
I'm trying to communicate between two FPGAs without using P2P streaming or any use of the backplane. We have two FlexRIOs, 7972R, two adapter modules for LVDS interfacing, NI 6583, and an infiband cable for port connections. Essentially, a handshaking sequence occurs and data is exchanged between the two RIOs.
RIO1: Output "ready" signal, input "SYNC", CLK and data
RIO2: Output "SYNC" CLK and data, input "ready"
When I run the attached code (Host code that controls the two FPGA vis), the input and output data do not match. I'm not sure if I'm missing something fundamental, or if the input is picking up noise from somewhere. I'm fairly new to LabVIEW so any direction would be greatly appreciated!
Thanks
07-06-2016
03:15 PM
- last edited on
01-08-2024
02:39 PM
by
migration-bot
Hi Alexaaguilarc,
Could you include your LabVIEW Project that includes the IO Modules and the FIFOs that you are using in your VIs? This will allow me to run your VIs in simulated mode.
Also, I noticed that a new service request was created for you. Is that regarding the same issue you mentioned here? If so, another Applications Engineer, Michael, will be reaching out to you shortly to help you troubleshoot the issue. I have notified him of this forum post so he can take a look at the attached code and information you have provided.
While he will help you with that, I want to point out some helpful getting started resources since you mentioned you are new to LabVIEW. It's possible you have already seen some of these but just in case you haven't, please see the links below for some recommended best practices.
Getting started with LabVIEW FPGA: https://learn.ni.com/learn/article/getting-started-with-fpga
How Can I Optimize/Reduce FPGA Resource Usage and/or Increase Speed?: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000PAJxSAO&l=en-US
NI LabVIEW High-Performance FPGA Developer's Guide: https://www.ni.com/en/support/documentation/supplemental/13/the-ni-labview-high-performance-fpga-dev...
07-06-2016 03:42 PM
Shalini,
Thanks for your reply and the provided resources! Yes this was also a service request, however I figured this out what was wrong with my program yesterday, so no additional help for this topic is needed.
Thank you!
11-29-2021 10:36 AM - edited 11-29-2021 10:37 AM
Hello Alexaaguilarc,
I am also facing the similar kind of problem, Kindly let us know how did you solved this issue.
Thank you