NI PCI 6534

[Vishal]

Hello friends i have faced some problems while working with 6534.
I am using two PCs having PCI 6534 in both of them.
I have connected all 32 data lines & ground lines of both. I am working with terminal box.I have connected REQ1 of first PC with REQ1 of second PC.
Problem 1 : In pattern Input Output mode i can acquire up to 20 MHz.But above 10 MHz i am getting data with errors.
On one PC(output side) i am running the vi continuous output
internal clock
REQ polarity i have defined at DIO config : active High with CPULL open
CPULL open
so as per vi given in labview it will transmit 0 to 255.

On second PC (input side)
External clock
CPULL open
REQ polarity i have defined at DIO config : active low with CPULL open

I am getting same data as it i
s being transmitted up to 10 MHz only. Above that frequency i am not getting proper data. What should be the reason?
Same problem occurs when i am using 8 bit or 16 bit operation. Pls provide me proper guidence.
It works exactly up to 10 MHz. If I am doin 10000001 also i am getting lossy data.

Problem 2 : In buffered pattern input -triggered example if i give 100 pre triggered points it gives me 101 pre triggered points with the same settings of REQ,clock & CPULL as in first problem on system 2.What can be the reason?

Problem 3 : In the same VI buffered pattern Input - triggered -
clock external
REQ polarity i have defined at DIO config : active low with CPULL open
when i use start trigger on pattern match with data pattern 20 decimal some times i get the first data 21. It should be 20 actually. Sometimes it gives 20 & sometimes 21. What may be the reason?

Please guide me to solve these problems.

My doubt for the 2nd & 3rd problem is that am i working properly by tra
nsmitting on rising edge & receiving on falling edge. Am i doing the right thing?

[rgharrison]

Hi Vishal,

When dealing with frequencies greater than 10MHz, you might see noise due to signal reflections and termination. These are high-speed problems that cause data corruption. To test if this is a problem, you can cable directly from 1 computer board to the other using the SH6868-D1 cable. This will ensure proper termination and a minimum cable length.

Another source of problems could arise from the generation occurring on the rising edge and acquisition occurring on the rising edge as well. At those speeds, you should acquire on the opposite edge that you are generating at. This can be done by altering the "request polarity" in the handshaking mode parameters of the DIO Config.vi.

As for your second problem, I'm not sure I am following yo
ur questions. You request 100 pre-trigger points and your buffer contains more points? How many points do you request total?

Your third problem probably has something to do with when you are sampling the data. Since it is your least significant bit that is changing and your program changes your least significant bit at a rate of 20MHz and your second least significant bit at 10MHz, you will get the exact same problem as in your first question. The point is, it triggers but by the time it acquires the sample, the least significant bit has already changed. This is because you are not meeting the hold time required between the trigger and the sampling of the data lines. If you play with the REQ polarity and sampling, you will be able to correct this issue.

Hope that helps. Have a good day.

Ron