11-20-2006 01:38 PM
Hello all,
I am using a 6562 board. It will be used for generation purpose only. I am trying to generate 4 things. A pixel clock, a line clock a frame clock and a 16-bit data.
The pixel clock is a free-running clock whose frequency can be set to between 10MHz and 40 MHz.
The line clock should be a 1 clock wide pulse that occur every 400 pixel clocks.
The frame clock should be a 1 clock wide pulse that occur every 10 line clocks. (4000 pixel clocks)
The 16-bit data should change on each pixel clock with some data.
I have to be able to set the bit in PFI 1, PFI 2 and DCC clk-out LVDS. I looked at the examples given under the niHSDIO directory and didn’t find much information on that.
Under the Dynamic Generation and Generation-Source Synchronous Example, which export its data active event to PFI 1 (from generation) and the acqusisition will receive the start trigger from PFI 2. But I don’t really understand it.
Basically, I would like to know how can I generate the above patterns to the PFI 1, PFI 2 and DDC clk-out LVDS.
I have been stuck for a while and really would like some help.
Thank you very much.
11-20-2006 02:21 PM
11-20-2006 04:28 PM
11-21-2006 09:43 AM
11-21-2006 11:40 AM
11-21-2006 01:23 PM
signalIdentifier | ViConstString | Describes the signal being exported. Defined Values
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11-21-2006 01:44 PM
"niHSDIO_ExportSignal(vi, NIHSDIO_VAL_MARKER_EVENT, "Marker1", NIHSDIO_VAL_PFI2_STR);"
If they are correct. I guess it is not case sensitive then, correct? (you can have marker0 up there and when call the exportSignal function, you can use Marker0)
Thank you.
11-21-2006 01:51 PM
11-21-2006 01:57 PM
11-21-2006 02:17 PM