PCI-6509 block read triggered by write task

[a440hz]

I'm using the PCI-6509, and I'm attempting to use a write task and a read task together, with the read task using change detection from the write task.

The write task is a simple Line Output type, and I'm reading from an array of 5120 uInt8 values: 1, 0, 1, 0, etc.--- in other words, a brute-force clock (since the 6509 has no real clock generation capability in HW). The write task output is physically connected to another port pin (in this case, Port3.0). BTW, I don't care about the clock being jittery. I just need rising edges, so the SW clock is OK for my purposes.

The read task is setup to read 2560 16-bit samples from Ports 1 and 2 with change detection from the rising edge of Port3.0. I'm using the 'N Samples' acquisition mode, with Samples to Read set to 2560. I'm using DAQmx_Val_GroupByScanNumber to interleave the bytes from Ports 1 and 2.

I've had very little success getting this to work; frequently, I hit the timeout error with timeouts on the order of 10 seconds! 2560 int16's or 5120 bytes should be able to be read in under 10 seconds.

I'm currently working around this problem by clocking in one sample at a time, which works well, but takes 0.8 seconds or so for each block of 2560 int16's.

How do I make the read task read 2560 samples with change detection? Please go into detail as to what order the API calls should be made, in addition to the task setup in MAX (or via the API).

[a440hz]

An update to my problem:

I have found that using the write task as a clock to trigger the read task only works when the number of rising edges from the clock task is much greater than the actual number of samples that I would like to read from the read task. For example, to read 2560 samples, I have found that 2560*11 clock cycles accomplish the entire read task. This is a problem, though, since the clock that I'm generating in software also controls some external FIFOs, and so I can't have the HW FIFOs and my read task out of sync.

In short, what's happening is that the write task (clock) is able to generate clock cycles faster than the read task can read samples, and so I'm missing samples.

Any of you are welcome to give me some sage advice about this problem....

Thanks in advance,

Joe

[Otis]

From what you're saying you're getting 2560 samples in 0.8 seconds (~3.2 kHz) out of a static DIO board. That's pretty impressive and I'm surprised you are seeing rates like that considering it is doing an operation that the board is not designed to do.

One thing you might want to do is look at the output lines and see if those lines are in fact changing at the rates you think they are. You might want to try looking at them with either a scope or another data acquisition board. While I know you are writing the data, there is a chance that since such operations at this speed are not the intended use of this board that you may not be actually outputting the signals at the rate you believe is occurring.

I would first verify that your signals are coming out as you expect.

If you need better timed DIO then I would recommend looking at the PCI-653X devices. They might serve your needs better than the Static DIO device that you are currently using.