PCI-7831R. DIO clock; available FPGA resources (BlockRAM, DCMs, global clock lines, etc.)

[postgrad]

I am evaluating the possibility of using PCI-7831R in a flexible test system.
I have to read a data burst from a digital bus at 40MHz. From your experience, is it possible to do this using LabVIEW FPGA Module tools, or is it better to use VHDL? Is it possible to generate the 40MHz clock for the external device?

How many Virtex-specific resources are available to the user (BlockRAM, DCMs, global clock lines, etc.)?


Thank you.
Sorin

[Luigi_B.]

Yes it's possible to generate and acquire 40MHz digital signal using 7831R and LabVIEW FPGA module.
The code could be compiled with different clock frequency speed.
The clock frequency available are:
40MHz
80MHz
120MHz
160MHz
200MHz

For example to generate a 40MHz pulse train you could compile with 80MHz clock frequency (2 clock pulses are needed for a square wave period).
Compiling with a clock frequency higher than the default one (40MHz) could give in some cases a compile error. These errors could happen more frequently if the code is more complex and needs more time to be executed.
To avoid compile error it's important to develop code in the best way.

I have attached an example developed in LabVIEW FPGA that generate 40MHz pulse train from DIO 0 and acquire the signal with DIO 1 used as a counter. The example was compile with a 160MHz clock frequency without any problem.

Regarding the Xilinx specification, you probably can find additional information looking on the Xilinx web site for the Virtex II family and in particular the model XC2V1000 (the model used on the 7831R) at this link:
http://www.xilinx.com/products/tables/fpga.htm#v2

hope this helps
Luigi