PWM signal with variable duty ratio

[dasika]

Hi ,

I would like to generate a PWM signal with variable duty ratio of frequency 500KHz on NI FPGA.

I have attached the FPGA VI file.  The code consists of two while loops in parallel. I am using FIFO to transfer data between two while loops.

The First while loop increments the duty ratio by 0.1 in every iteration and the value is written to FIFO. ( The duty ratio is reset to zero if it is greater than 1).

The second while loop reads the duty ratio and generates the PWM signal.

The problem I am facing is that the duty ratio is not getting updated and the PWM output signal is of 250 KHz instead of 500KHz.

I have verified the PWM code and it works fine when I am using a single while loop i.e., I get the 500KHz signal with the desried duty ratio (While--3).

I am not able to locate the fault. Can anyone help me with same ?

Thanks,

Deepti

[LuisYO]

Hi there

First of all, which HW are you using?

There are some strange things in your code:

-The timeouts:

Your FIFO memory stops waiting data only 100 ticks after it started to wait... why? If there's no a reason, you can use a -1 value wired to timeout to make the FIFO to wait undefinetely as both cycles depend on those FIFOs, so no timming probles would appear.

-The cycle loops:

You are using cycle loops inside flat sequence (flat sequence is not recommended in LabVIEW programming) instead of tick count nodes. Remember cycle loops waits untill the machine clock (in ticks) retrieves a value which is multiple of the wired value. If the machine clock is 160 (for example) when the flat sequence starts to run (ignoring structure's overhead), the cycle loop will wait nothing because a multiple has been already reached.

-Parallel Whiles

Why are you using different while cycles to achieve a PWM?

The only way you can sync parallel processes when programming for NI FPGAs is using occurrences or local variables inside a single frame of a flat sequence structure. Using a -1 wired to the timeout of the reading FIFO method could work too.

Hope this helps... see you!

[dasika]

Hi,

Thanks for the response.

1. I am using NI cRIO 9082 and the C series module NI 9401.

2. Timeout : 100 ticks

I realized that and changed my sampling time to -1. But even then I face the same problem.

3. Cycle loops:  I didn't quite understand what your trying to say.

Are you suggesting to use tick counts instead of wait in flat sequence to generate PWM ?

Is it recommended to use looptimer in a while loop to control the execution rate of the loop ?

4.  Parallel Whiles

I am new to LABVIEW Programming. Can you please suggest if there is a better way to generate PWM Pulses without using Parallel while loops ?

Thanks once again for the response. I appreciate your help.

Deepti

[dasika]

Hi

I have attached a file to generate PWM signal.

Is this programming method better than my previous version ?

Thanks,

Deepti

[LuisYO]

Hi Again!

Before looking deeper I want to know how are you measuring the output frequency? None of your codes include a way to make the signal measurable...

About the problem you have of getting a 250kHz freq instead of the 500kHz one, it has a very simple explanation. I've attached an image of a generic PWM (capture.jpg), le tme explain:

• You've set the Tpwm (Pwm Period) to 80 ticks to get a 2us period, this is 500kHz period considering the 40MHz clock cycle. Wiring the 80 value to the Loop Timer makes the While Loop to execute the code within every 80 ticks, if you make the boolean value to toggle every cycle, then it will be in high possition for 2us and in low possition for 2us, giving the unwanted 250kHz PWM
• The FPGA must has its own Tfpga (FPGA period), it must be shorter than the Tpwm so the high and low states can be calculated. For example if you set the Tfpga to be 1us, and you toggle the binary value, then you'll get a 500kHz 50% duty cycle signal. Making the Tfpga to be 100 times shorter that the Tpwm would let you, for example, to separate the Tpwm in 100 parts so high and low states can take an integer value from 0 to 100, this is, the duty cycle could be chossen from those integer values.
• I've included as attachment a snippet (Look in the forums if dont' know what it is) of a program that can do a varying duty cycle pwm (Increases and decreases) of 4kHz (250us Tpwm / 2.5us Tfpga). There is also attached a capture of the program performance when changing from decreasing to increasing and its associated PWM.

I'm not sure if you can accomplish a 500kHz PWM with the 40MHz clock, it depends on what operations you want to make inside the while loop.

There is also a block named Square wave which can help you to make a quick PWM with your cRIO.

Let me know if you have more doubts

See you!

[dasika]

Hi

1. I am using  oscilloscope to measure the output frequency.

2. The vi I posted didn't have enough comments to explain clearly.

80*duty ratio gives number of ticks the PWM is supposed to be in high state. So the output stays in high state for 80*dutyratio.

Then the logic is toggled. Now it stays in low state for 80*(1- duty ratio)  ticks.

3. It is possible to generate 500kHz PWM signal. The while --3 in the vi generates 500kHz PWM signal.

As suggested by you previously, I am using local variables in single frame to transfer the data between while loops. It works fine. I able to generate 500kHz signal with variable duty ratio.

Thanks once again.

Deepti