Dear Community
I have a problem with the timing of an SCTL in an FPGA Target (MyRIo 1900):
Backgound: I'm writing a FPGA Driver for a SPI interface. During that I observed, that the FPGA is NOT measuring the input of a DIO Line Correctly. The Osciloscope shows the correct output Level from the slave on the MISO line. The MyRIO is creating the clock line. On the rising edge of the Clock (which is created by the FPGA of the MyRIO) the value of the MISO Line should be stored. This happend two ticks after the rising edge of the clock.
Out of that, I created a very simple code: I have three DIO Lines - two outputs (DIO6, DIO7) and one input (DIO5). DI5 and DO6 are briged physically together (See Connection Diagram attached). DO6 gets the level from top-Level (RT_Main VI). The rising Edge on DO6 is given physically to DI5. This level is measured in the FPGA and the output is given to the DO7. The Lines DO6 and DO7 are connected to the Osciloscope. The Main VI is just switching DO6 on and off all the time.
What I expected to see on the Osciloscope is a delay from one tick between the rising Edge on DI5 / DO6 and the rising Edge on DO7. But there are three ticks between.
One ticks delay is explainable, because I do not know the "connections" of the compiled VHDL Code. So the rising egde on DO6 could not bee seen in the same tick from the DI5 pin. But latest in the next tick it should be seen, because on the oxciloscope, the nput level of this pin is high already. But it take another two ticks, until the DO7 Line shows this level.
The paradigm of the SCTL, that it executes within one clock cycle (25ns in that case) is violated in my eyes. WHY IS THAT SO?
The RT-Main (RT_Main2.vi) and the FPGA Code (Debug_False_SCTL.vi) is attached. Also attached is the connection Diagram (how the three DIO's of the FPGA are connected with each other and the Osciloscope). The KO.jpg image shows the Code during execution an the Output of the Osciloscope.
I am very thankful of any constructive help :-).
Kind Regards, Thomas
