01-03-2012 07:19 AM
I'm using a FlexRIO PXIe-7962R board with a NI 6581 Module Adapter using a Port type CLIP and Labview 2011.
I would like to use CLOCK OUT from DDCA to a syncronize data exchange with my external device connected to DDCA and DDCB.
As suggested on Module Adapter Documentation i took as example the project 'NI 6581 Continuous Generation - Internal Clock.lvproj'.
I placed DDCx_Porty_Write and DDCA_clockOut_Enable write methods inside a SCTL as shown in the following figure.
What I can see, by connecting my oscilloscope to output ports, is that CLOCK OUT Signal starts switching after some data have already been written to ports, and not simultaneously with the first data values as shown in the folowing figure.
At the end of data transfer DDCA_clockOut_Enable Signal is pulled down by FPGA code, but CLOCK OUT signal freezes for a while to high value.
Is there any way to avoid this kind of behavior and have CLOCK OUT signal active with first data values on output as shown in the following picture?
01-10-2012 11:56 AM
Hello,
Have you tried to insert the code of the bigger while loop inside the single cycle while loop of the case structure?
01-11-2012 04:45 AM - edited 01-11-2012 04:47 AM
Hello A.V.,
i tried to insert the code of the bigger while loop inside the single cycle while loop of the case structure, but unfortunately nothing changes.
I've found a way to obtain the desired result, but it's not satisfying me because always raise an FPGA error:
1) I Developed an external VHDL CLIP with a conditional enable input, in order to control the clock driving the SCTL.
2) I placed the SCTL outside the bigger while loop.
3) I drove the CLIP conditional enable input with 'Fire Enable' control from within the bigger while loop.
4) The signals were synchronous but on 'Fire Enable' toggle the vi gave 'Clock out of range' exception for the clock driving the SCTL, raising up a Labview Error.
thank you for the suggestion,
Marco.