Write and read on trigger 653x

[zoran]

I have 6533 digital I/O and 6602 timing I/O board. I have to send 7 channels out for the first 24 clocks (25600Hz) and then read one channel back, after 24 clocks for the next 1224 clocks. It should repeat this every second. I was able to make vi which is doing this (see attachment) and it writes once every second but reads back only once after I start vi. How I can make it to retrigger - in my case when it gets signal on ACK2(STARTTRIG2).

I used your example Cont Handshake Output.vi as a starting point. What is a purpose behind a logic to send half a buffer at the time. Why don�t send the whole thing every time?

Thanks,

Zoran

[rgharrison]

Hi Zoran,

The best way to accomplish this, I believe, is to set up 2 groups on your 6533 board. The first group will be for output and the second group will be for input. You will want to use the continous pattern generation and acquisition type examples (pattern I/O).

The key is to use an external clock for both your output operation and your input operation. Since you have both the 6533 board and the 6602 board, I would use the 6602 counters to devise the complex timing you need and use this to clock your 6533. You could use two counters to create a retriggerable finite pulse train. Your finite pulse train would clock 24 clocks at a frequency of 25600Hz. The example below demonstrates retriggerable finite pulse generation. You would then have another counter generating a 1Hz pulse train which would trigger this finite retriggerable pulse train every second. The result is that on the output you would have a signal that has 24 rising edges every second at a frequency of 25.6kHz. Similarly, you could use another 2 counters to generate the signal needed for the input signal. You could use the same counter generating the 1Hz signal for these two counters as well.

The basic setup for a retriggerable finite pulse generation (using 2 counters) is the following.
1) Configure your first counter for retriggerable pulse generation which is an application type.
2) Set the Gate of this counter to be the output of the counter generating the 1Hz signal.
3) The source should be the 80MHz timebase.
4) Your pulse specs would be 2 source edges for the delay (which is the minimum)and (1/25600 x 24) x 80MHz, which will give you the number of 80MHz edges for that period of time, for the pulse width. This counter will then be applied to the gate of the following counter.
5) Configure a counter for pulse generation and generate a pulse train at 25600Hz. It will be gated by the previous counter.

You would apply the same steps to configure the other two counters for the same application. This time you would set a delay greater than 2 80MHz pulses. You would want it to be 2 + x where x is the number of pulses in terms of delay which represents the start of your input of the 1 channel.

In total, this complex triggering will require 5 counters to accomplish. Hope this helps. Have a good day.

Ron
Applications Engineering
National Instruments

[zoran]

Thanks Ron,

Your answer works for pulse generation, but how I can make retriggerable input. I tried using example Cont Pattern Input but it reads only once when is connected after DIO Write (see vi I sent). I have wire going to STARTTRIG2 and it toggles every second but nothing got read into DIO Read.

Zoran

[rgharrison]

Hi Zoran,

My idea about using the counters is to use them as the clock for you application. This means you wouldn't need to use the STARTTRIG line. The counter output would be used as an external clock to your REQ line.

Ron