cRIO SPI

[brian_d]

I am new to LabVIEW and the cRIO hardware.

Part of my application will require communication to a couple of SPI devices and I am trying to port the spi_dual_port_example project over to this hardware. I have tried two meothds so far, the first is to simply create an FPGA project and then add the VI files from the example to it. The second was to create a new project using the New | Targets and Devices.

In either case, when I try to add  my signals using New | FPGA IO, I get a window that says No Resources Available. The instructions for the example imply that the selections for a setup other than the one it was written for might show different options but would be similar.

Has anyone else used this example for a different target system and if so, what kinds of modifications did you require to use this?

Thanks,

Brian

[Drew_T]

Brian,

What cRIO are you using?  What modules do you have inserted?  Any modules you inserted before you added the chassis should already show up under the chassis and the IO should be under the FPGA target.

If you instered it after it was added, or if would like to simulate a C-Series module to develop your application, you can right click the FPGA Target and select New » C Series Module.

Good Luck,

[ferra_17]

Hola.

    Tengo un compactRIO con serie 9205 y 9264 soy nuevo en esto megustaria saber como puedo hacer un programa para generar una onda cuadrada senoidal y en este sistema y trabajarlo en FPGA alguien me puede ayudar?

[brian_d]

Drew,

At the moment I am using cRIO-9111 with a NI 9401 Digital IO module. This is a demo that I borrowed from our Sale Engineer to start my development before my cRIO-9074 (also with two NI 9401 modules) arrives. The connection to the FPGA in the version of the SPI that I downloaded uses FPGA IO ports that are called CS, SCLK, MOSI and MISO. I was told that these are not correct for my setup and that I should create FPGA IO Nodes for these signals in their place. Doing so results in there being some disconnects that there doesn't seem to be a way to repair.

Attached is the VI module I am trying to change. Any ideas?

Thanks,

Brian

[Drew_T]

Hi Ferra_17,

I don't speak spanish, but I translated the text and it appears you are trying to get started with a cRIO and the 9205.

Here are some great resources:

http://www.ni.com/gettingstarted/setuphardware/

https://decibel.ni.com/content/docs/DOC-1260

https://decibel.ni.com/content/docs/DOC-9741

[Drew_T]

brian_d,

I looked at your VI, and once it was under my FPGA target in a new project, all I had to do was delete the wire and rewire the terminal.  Sometimes when replacing blocks on the diagram, wires aren't routed correctly.  Try this and let me know what you find.

[ferra_17]

Hello.
        Stoy working with a RIO 9012 and 9205 and 9264 series and seeking examples of how to make a square wave or sine FPGA. Anyone can help me?

[Drew_T]

ferra,

This is not related to the question asked in the thread.  Please keep threads to one question only.  That said, see the following express VIs for info on getting sine and square waves in FPGA.

http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpga/sine_generator/

http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpga/fpga_square_wave/