external clock & finite input limit

[Vishal]

Hello friends, I have some questions and some donfusion with pattern generation NI PCI 6534.
1.) Is there any limitation over external clock?i.e. can we give more than 20MHz external clock? If NO, why?
2. ) why it is prefferable to use less than 32MB size of data in finite operation? Because as per me, in pattern input as 6534 acquires samples it stores to 6534 onboard memory and at the same time passes to PC buffer through DMA FIFO. So after 32MB acquired, onboard memory will be overwritten from the first memory location and still it should be possible to continue the operation.

[rgharrison]

Hi Vishal,

I can probably help out with this...
1) Yes, there is a limitation of the external clock. The maximum rate is 20MHz. This rate is dependent on 6534's DIO chip internal switching characteristics. These characteristics have to do with how the latching structure (silicon structure used to capture data) is designed and the elctrical characteristics of the semiconductor's material (electrical characteristics of the material). The spec for this chip outlines the following: the cycle time be at least 50ns and the high/low time must be between 20-30ns.

2) For finite acquisition it is always advisable to have a buffer size of less than 32MB since this is the size of the onboard FIFO. It garrantees that you will acquire all data at the maximum rate si
nce no PCI transfers are necessary and it is only dependent on the board hardware and not the whole computer system. As you pointed out though, it is not necessary to be limited to this size. Benchmarking for rates was conducted using a 1GB finite acquisition buffer size which is much greater than the 32MB buffer. It relies on the DMA transfers clearing some of the buffer so that it could acquire more. For rates checkout the following knowledge base:

Performance Benchmarks For The High-Speed Digital I/O - NI 653x
http://digital.ni.com/public.nsf/websearch/4FCA248D888831C386256D8900563E45?OpenDocument

Ron