Hi John,
There are a couple issues with that example. The first is that you must have the "acknowledge modify mode" parameter set to "delay". This will alow you to modify the "internal PCLK frequency" parameter. Another issue noted is that there is a situation with the driver in which the first 11us set at another frequency will still be at 20MHz but the rest of the samples will be acquired at the desired rate (3.33MHz for example). Therefore, you will have to be bursting more than 220 (11us at 20MHz) samples to see your specified PCLK rate. Hope that clears things up. Have a good day.
Ron