serdes channel serial aquisition and generation

[incisive]

Hi
I am confused regarding the usage of serdes channel clip.
I need to both acquire and generate lvds serial bitstream and save it in 0 and 1 form i.e.
1. read a tdms file of 2 channels with 1,0 bitsream data.
2. acquire serial bitsream from external 2 channels and save it in tdms file.
As far as I know, the serdes channel clip aquires U16 data on each channel. then combines 10 bits keeping 6 unused and outputs that on port. How do I prevent each channel from deserializing..and simply save the bitsream in tdms file. I want my lvds data in 0, 1 form.
Can the serdes be disabled?
If not..how do I serialize my stream? is there a code which can help?

[Kelly_B]

Hi incisive,

I believe I can address a few parts of your question.

1.  Modifiying the existing CLIP is not supported, so if you choose to go that route NI will not be able to provide assistance.  I strongly recommend you do not modify the existing CLIP.

2.  It sounds like the Serdes Channel CLIP may not be best for your application.  For example, the Basic CLIP for this hardware provides 16 bidirectional lines and does not perform any serialization on the lines.  This may be more appropriate for your application.

Please let us know if you have any follow up questions by posting in the original thread.  Our community guidelines recommend keeping one question within a single thread to allow the community to respond more efficiently.  Also, questions regarding FlexRIO are best posted in the Real Time Measurement and Control board, as was your original post on this issue.  http://forums.ni.com/t5/Real-Time-Measurement-and/ni-6587-serdes-channel-serial-input-output/td-p/32...

Please let us know if you have additional questions.

[incisive]

Thanks a lot. I tried using the basic connector but I am not able to aquire LVDS clock on basic connector.My clock is 50MHz. the system gives the error of external clock not detected. I used IO module clock 1 as external clock and set properties on adaptor module. In another 40 MHz timed loop i enabled xpoint switch write and selected strobe bypass as input to io_module_clock_1_source. why is my clock not acquired?

[Kelly_B]

Hi incisive,

Based on the documentation for the Basic CLIP, there are both clock input and clock output lines available.  You can read more about it on page 11 of this manual: http://www.ni.com/pdf/manuals/375614b.pdf

Do you have a screenshot of the code that you are working with, and of the error message?

[incisive]

the error I recive is

An error was detected in the communication between the host computer and the FPGA target

 the clock is detectedd in case of serdes channel clip but not in basic connector clip  

I even used a while loop before the timing delay for configuration of xpoint switches..yet my clock is not detected

[Kelly_B]

Hi incisive, 

This clock error is common when the clock is not fully turned on and running before the FPGA is running.  What purpose is the external clock serving in your application, what is it synchronizing your application to, and what is the source of your clock?