About second TIO location for M Series

[Ash.OK]

Hello,

I'm thinking about using both counter 0 and 1.

According to all samples about gpct, that are included in M Series, tTIO object should be initialized with

passing the timer located address like this:

    bar1 = bus->createAddressSpace(kPCI_BAR1);
    boardM = new tMSeries(bar1);
    board = new tTIO(bar1);
   
    //TIO chip on MSeries boards is at offset 0x100
    board->setAddressOffset(0x100);

It says TIO offset is at 0x100.

On the other hand, I refer 660x sample for that I understand it would compatible in between.

In the 660x sample (gpct_ex9.cpp), it looks like describing 2 counter-use method like this:

  tAddressSpace  cardSpace,cardSpace2;
  tTIO *tio,*tio2;

  //The first TIO is at BAR1+0x0, the second TIO is at BAR1+0x800
  cardSpace = bus->createAddressSpace(kPCI_BAR1);
  cardSpace2 = bus->createAddressSpace(kPCI_BAR1);

  tio = new tTIO(cardSpace);
  tio2 = new tTIO(cardSpace2);
  tio2->setAddressOffset(0x800);

According to the 660x sample, the second TIO is at offset 0x800.

Is there anyone who can tell me how to use the second TIO for M Series?

Thanks in advance.

Ash.

[Tom_W_[DE]]

Hi Ash-

There is no second TIO for M Series- all of the functionality is included in the single TIO-like "package" in the STC-II via the G0 and G1 bitfields and registers sprinkled throughout.  There are only two general-purpose counter/timers (G0 and G1) on the M Series devices.

Hopefully this helps-

[Ash.OK]

Hello Tom

Thanks I've got it. That's enough for me to know about this issue.

Thank you.

Ash.