Clocked M-Series DIO

[spg]

Hi --

I'm working on a driver for M-Series devices (starting with 6221). I have basic timed AI working; my next time is to implement digital output that is correlated with my AI sampling clock. As a first shot, I'd like to just toggle one i/o line with each CONVERT signal.

I understand roughly how to do this, but am guessing it will take me a while of trial and error to figure out the proper register setup. Does anyone have a few lines of sample code (a la dioex1.cpp, aoex1.cpp, etc.) that would nudge me in the right direction?

thanks!

--spg

[DiegoF]

Hi spg,

At the moment, there are no correlated DIO (CDIO) examples.  However, since CDIO can only use external timing signals, configuring the CDIO engine is simple, at least compared to AI or AO.  These registers should get you started:

// reset CDO engine

board->CDIO_Command.writeCDO_Reset(1);

// CDO configuration
//    see tMSeries.h (tCDO_Mode) for more options

board->CDO_Mode.setCDO_SAMPLE_CLK_Source (tMSeries::tCDO_Mode::kCDO_Update_Source_SelectAI_Convert);
board->CDO_Mode.setCDO_SAMPLE_CLK_Polarity (tMSeries::tCDO_Mode::kCDO_PolarityRising);
board->CDO_Mode.setCDO_FIFO_Mode (tMSeries::tCDO_Mode::kCDO_FIFO_ModeFIFO_Half_Full);
board->CDO_Mode.setCDO_Halt_On_Error (kTrue);
board->CDO_Mode.setCDO_Retransmit (kTrue);
board->CDO_Mode.flush ();

// set which lines are controlled by the Correlated DIO engine.
//  0: Static DIO
//  1: Correlated DIO

board->CDO_Mask_Enable.writeRegister (cdoMask);

// update direction mask
//  0: Input
//  1: Output

u32 directionMask = board->DIO_Direction.getDIO_Direction (); // get softcopy
board->DIO_Direction.writeDIO_Direction (cdoMask | directionMask);

// arm CDO engine

board->CDIO_Command.writeCDO_Arm(1);

// ----------------------------

// Fill the FIFO ...
board->CDO_FIFO_Data.writeCDO_FIFO_Data(data); // 32-bits

// ... and use status registers to determine the FIFO state

board->CDIO_Status.readCDO_Underflow_St ();
board->CDIO_Status.readCDO_Overrun_St ();
board->CDIO_Status.readCDO_FIFO_Request_St ();
board->CDIO_Status.readCDO_FIFO_Full_St ();
board->CDIO_Status.readCDO_FIFO_Empty_St ();

// ---------------------------

//  To stop

board->CDIO_Command.writeCDO_Disarm(1);

Hope this helps,
Diego

[spg]

Diego --

Awesome! Below is the exact code (based on yours) that worked for me. It just toggles p0.0 and p0.1 at the ai_convert clock.

Thanks very much for your help.

--spg



board->CDIO_Command.writeCDO_Reset(1);

board->CDO_Mode.setCDO_FIFO_Mode(tMSeries::tCDO_Mode::kCDO_FIFO_ModeFIFO_Half_Full); // doesn't matter yet

board->CDO_Mode.setCDO_Polarity(tMSeries::tCDO_Mode::kCDO_PolarityRising);
board->CDO_Mode.setCDO_Update_Source_Select(tMSeries::tCDO_Mode::kCDO_Update_Source_SelectAI_Convert);
board->CDO_Mode.setCDO_Retransmit(kTrue);
board->CDO_Mode.flush();

board->CDO_Mask_Enable.writeRegister (0x3); // bits 0 and 1
board->DIO_Direction.writeRegister (0x3); // bits 0 and 1 output

board->CDO_FIFO_Data.writeRegister(0x02);
board->CDO_FIFO_Data.writeRegister(0x01);

board->CDIO_Command.writeCDO_Arm(1);

[fmhess]

I am curious what the data lane bits do in the CDI_Mode and CDO_Mode registers? Your example code doesn't seem to use them. All I can find about their meaning is the following enum from the tMSeries.h header:

typedef enum {
kCDI_Data_LaneCDIO_15_0 = 0,
kCDI_Data_LaneCDIO_31_16 = 1,
kCDI_Data_LaneCDIO_7_0 = 0,
kCDI_Data_LaneCDIO_15_8 = 1,
kCDI_Data_LaneCDIO_23_16 = 2,
kCDI_Data_LaneCDIO_31_24 = 3,
} tCDI_Data_Lane;

which seems to suggest they select either a byte or word of the 32 bit dio port for some purpose.

[Tom_W_[DE]]

Hi Frank-

Those settings are used to allow for data compaction for CDIO operations where the full 32-bit port is not used.  For example, you might want to use this for the 62x0 or 62x1 devices where only 8-bits are available on port0 (the correlated dio port).

Under normal conditions (including those shown in the DDK examples) we would read or write 32-bit samples for each port value, regardless of whether the port (or lines in use) are 8- 16- or 32-bits wide.  This setting would most likely help if PCI throughput was a problem on the device, but we don't have examples for the DDK and as far as I know NI-DAQmx does not use this hardware mode either.  So, I wouldn't worry about making this setting assuming you're getting the performance you need from the examples as written.

Hopefully this helps-