Counterswap on a NI-6602

[ben_]

Hello,
I am programming a NI-6602, register level programming.
Programmed this card before, e.g. "pulse width measurement", works fine.

Now, I want to program "continuous pulse trains" on all 8 channels.
But I only can get pulses from 4 of the 8 channels, either TIO(0) or TIO(1).

I follow example 9 from the HDDK.
It seems that the CounterSwap bit, of the ClockConfigRegister, (TIO(0):0x73C and TIO(1):0x73C+0x800), switches all (!) output-lines (PFIn). And not just the outputs for it's own TIO.

Does anyone have experience with this?
Who can help me?
Thanks, Ben.

[Anonymous]

Ben,

The 6602 actually needs a different MITE initialization sequence from
all other NI PCI/PXI boards. If you use the normal sequence, and
write to TIO1, both TIO0 and TIO1 will be written.

The correct sequence is:

//Tell the MITE to link the BAR1 address to the DAQ Board
//You must initialize the MITE before you write to the rest of the PCI
board
void initMite(iBus *bus)
{
tAddressSpace Bar0;
u32 physicalBar1;

//Skip MITE initialization for PCMCIA boards
//(which do not have a MITE DMA controller)
if(!bus->get(kIsPciPxiBus,0)) return;

Bar0 = bus->createAddressSpace(kPCI_BAR0);

//Get the physical address of the DAQ board
physicalBar1 = bus->get(kBusAddressPhysical,kPCI_BAR1);

// ***** 6602/6608 specific MITE initialization *****
// Hit the
IO Window Base/Size Register 1 (IOWBSR1) in the
MITE. We set the
// address, enable the window and set the size of the window:
Bar0.write32(0xC4, (physicalBar1 & 0xffffff00L) | 0x8C);

// Write to the IO Window Control Register 1 (IOWCR1) to make
the IO window
// go to RAM memory space instead of the config space
Bar0.write32(0xF4, 0);

// ***** End of 6602/6608 specific code *****

bus->destroyAddressSpace(Bar0);
}

[Anonymous]

Tim,

Thanks, this helped me. Now it works fine.
I did not know this 6602 board needed a different MITE initialization
sequence.
There seems to be mistakes in the RLPM.

In the RLPM (660x Register-Level Programmer Manual, April 2002
Edition) there seems to be a mistake on page 3-44:
There is stated: Write32(BAR0 + 0xC0, (BAR1 & 0xFFFFFF00L) | 0x80)
this must be : Write32(BAR0 + 0xC4, (BAR1 & 0xFFFFFF00L) | 0x8C)
!!!

Furthermore, in the RLPM the "IO Window Control Register 1" (IOWCR1)
and its setting is not mentioned.
In the RLPM must be added: Write32(BAR0 + 0xF4, 0)

I wonder where this IOWCR1 register is documented..

[douglas_9]

There is an updated version of the manual labelled November 2002.

It is at http://www.ni.com/pdf/manuals/370505b.pdf