Digital I/O functionality of the PCI-6602 RLP

[yechiel]

Customer wants to use more of the Digital I/O functionality of the PCI-6602 .

They already use successfully the first 8 digital I/O lines of the card (PFI_0 - PFI_7), as inputs, but need to use some additional Digital I/O lines (currently for Outputs).

From reading the 660x User Manual and the Registers Level Programmer Manual, it seems that it may be possible to use the following additional lines for this purpose:

PFI_9

PFI_13

PFI_17

PFI_21

1. Could you instruct us how to use these 4 lines as Digital Outputs? Please note that we use our own device driver ( through RLP ) and have direct access to the card's registers.

Please show us how to enable and disable the output of each of these lines (individually), and how to change each of the line's output logic level.

It would be nice if you could send us a sample program that demonstrates the required steps.

2. In the future, we may want to use some of these lines as Digital Inputs. Could you instruct us how to do this?

3. ) In the future, we may want to use some additional Digital I/O lines. We saw that the card contains 4 additional lines that can function as Digital I/O: PFI_11, PFI_15, PFI_19 and PFI_23.

Could you instruct us how to use these lines, both as Digital Outputs and as Digital Inputs?

Yechiel

[JoeFriedchicken]

Hi Yechiel,

I believe it will be possible to show you and your customer how to achieve their goals. As I've posted elsewhere [1], I didn't design the TIO chip, and so I need to speak with a few colleagues to learn more about the routing matrix.

[1] What are the 3-bit field choices for Hw_Arm_Sel in PCI-6601
https://forums.ni.com/t5/Driver-Development-Kit-DDK/What-are-the-3-bit-field-choices-for-Hw-Arm-Sel-...

[JoeFriedchicken]

Hi Yechiel,

After some reading, I've learned that I need more information about how the first 8 DIO lines (PFI0..7) are currently being configured. What registers and what values are you programming?

In addition, I would like more information about the application. I don't know if your DIO is software-timed (static) or hardware-timed (correlated). What is the card connected to, and how is it being used?

Once I get a better understanding of your needs, I'll be able to give good advice about how to use more lines for DIO. I will not, however, be able to provide an example program to demonstrate the required steps because my test machine is currently being used for another project. Instead, I can give some pseudo-code and guidance about how and when to program the registers.

[ItaiH]

Hello,

We use the first 8 PFI lines (PFI0..7) as digital inputs (We use the STD DIO Parallel Input register to read their values).

We also use PFI lines 10, 14, 18, 22, 26, 30, 34 & 38 (Gates). We drive external signals to these lines. These signals are used to generate interrupts (which are handled by our device driver).

We configure PFI lines 8, 12, 16, 20, 24, 28, 32 & 36 as counter outputs.

All other PFI lines are unused.

We would like to be able to use some of the remaining 12 PFI lines that can be used for Digital I/O (i.e. PFI lines 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31), initially for digital output, and later for digital input (we may also need to use some lines for output and other lines for input).

Our software determines when to write or read the digital I/O lines (not hardware-timed).

Can you send us insructions how to:

1. Enable the DIO output of these PFI lines.

2. Change the output level from low to high, and from high to low.

3. Read from these digital I/O lines.

All using RLP.

Thanks,

Itai

[JoeFriedchicken]

Hi Itai, and welcome to the DDK forums 🙂

Thanks for sharing more about your application and current usage of the PFI lines. The PFI lines are dual-purpose: they provide access to the counters, but can also act as a correlated digital I/O port. The documentation is unclear whether or not these pins can be mixed among both modes, and since I don't have a test machine available, I have no way to verify if this is the case, but I have a feeling it should work. At any rate, let's dig into the bits 🙂

Since you're using other PFI lines for gating and output in addition to the STC DIO lines, you're already programming the IO Config Reg registers to set the lines for gates or output. All you need to do is program the registers that correspond to the remaining PFI lines that you want to use for static DIO as either input or output.

The 660x RLP manual [1] has good documentation on which registers and bit fields to use beginning on page 3-53 (or 87 in the PDF). It says how to program a PFI line to be a digital input or counter output, but doesn't say how to program the line to be a digital output. If you write 0d3 (0b10) to the Output_Select field, the line will be programmed as digital output. And as the RLP manual says, writing 0d0 (0b00) to the Output_Select field puts the pin in a Hi-Z state, disabling output.

Okay, now that the direction of the pin has been configured, the next step is writing or reading data depending on the direction. This is more complicated because the other 32 DIO lines that aren't in the STC DIO lines are designed for correlated output using one (or two, depending on the complexity) of the TIO's counters as the clock. Software-timed updates are possible, but require more register I/O. Output is a bit easier to describe, so I'll start with that first.

For static output on the correlated digital lines, you'll need to program three registers.

1. TO_StrobeReg at offset 0x500
2. TO_ConfigReg at offset 0x504
3. TO_InitValReg at offset 0x510

TO_StrobeReg at offset 0x500

TO_StrobeReg is 32 bits wide, and has these fields:
30: TO_SWEnable
29: TO_SWDisable

Writing 0b1 to TO_SWEnable will enable output generation, and writing 0b1 to TO_SWDisable will stop output generation.

TO_ConfigReg at offset 0x504

TO_ConfigReg is 32 bits wide, and has these fields:
13..12: TO_StopMode
2..0: TO_Format

Set TO_StopMode to 0b00 to tell the TIO to stop generation on the state of TO_SWDisable.

Set TO_Format to 0b010 to tell the TIO to use immediate updates on the output pins.

TO_InitValReg at offset 0x510

TO_InitValReg is 32 bits wide, and has only one field:
31..0: TO_InitVal

This field holds the data that you want to output. Since you're using the STC DIO lines, the first 8 lines of this field are ignored, and so PFI 8 is the first usable line.

It's possible that the TO_InitValReg is the only register you need to program in order to perform static updates, but I included the other registers and fields in case it's not. Again, since I don't have a free test machine, I can't verify which registers are needed. I would write a simple program to test the digital output behavior before adding it to your current application. If you run into problems, it will also be easy for me to make suggestions and corrections if you have a such a program.

Message Edited by JoeFriedchicken on 11-19-2009 11:54 AM

[JoeFriedchicken]

For static input on the correlated digital lines, you'll need to program several registers. Actually, 'pure' static input isn't possible on the correlated DIO lines, so you will need to send a clock tick each time you want to latch the state of the input lines. Hence, there are few more registers to program.

Sampled_DI_Config at offset 0x730
Sampled_DI_High at offset 0x734
Sampled_DI_Low at offset 0x738
TG_0_LevelEdgeReg at offset 0x660
TG_0_CombinationReg at offset 0x6A0

Sampled_DI_Config at offset 0x730

Sampled_DI_Config is 32 bits wide, and has this field:
2..0: Trigger_Sel

Set this field to 0b00 to use the first internal trigger as the latch signal.

Sampled_DI_High at offset 0x734

Sampled_DI_High is 32 bits wide, and has this field:
7..0: IO_In_39:32

Once the trigger has latched the data on the lines, read this field to retrieve the states of I/O pins 39..32. So, bit 7 of this register corresponds to PFI 39, and bit 0 corresponds to PFI 32.

Sampled_DI_Low at offset 0x738

Sampled_DI_Low is 32 bits wide, and has this field:
31..0: IO_In_31:0

Similar to the Sampled_DI_High register, this register holds the latched data for the lower 32 I/O pins. Bit 31 of this register corresponds to PFI 31, and bit 0 corresponds to PFI 0. Remember that since you're using the STC DIO lines, the lower 8 PFI lines are ignored.

TG_0_LevelEdgeReg at offset 0x660
TG_0_CombinationReg at offset 0x6A0

You need to use these registers to simulate clock ticks whenever you want to latch data into the board. I described how to use these registers in another post [2]; follow those instructions and then make the following two changes. First change: for LESel, write 0d63 to choose an always low trigger.

The actual clock simulation happens in TG_0_CombinationReg. Second change: in the CombFunction field, write 0b0000 to set the trigger state to low. When you want to latch data, write 0b1111 to set the trigger state to high, then set it low again to prepare for the next clock tick. On the rising edge of the trigger, the board will latch data and you can read it with the Sampled_DI_* registers.

[JoeFriedchicken]

Phew! So there is all the low-level information you will need to use your left over PFI lines for static DIO. The overall procedure is:

0. Program the direction of the PFI lines as input or output with the IO_Config_Register.

For output:

1. Program the TO_ConfigReg register.
2. Program the TO_InitValReg register.
3. If necessary, use the TO_StrobeReg register to enable/disable output generation.
4. Update the TO_InitValReg register as needed.

For input:

1. Program the TG_0_LevelEdgeReg register.
2. Program the TG_0_CombinationReg register for low trigger state.
3. Program the Sampled_DI_Config register.
4. Program the TG_0_CombinationReg register for high then low trigger state.
5. Read the Sampled_DI_* registers to retrieve the latched data.

[1] NI 660X Register-Level Programmer Manual
https://www.ni.com/docs/en-US/bundle/ni-660x-register-level-programming-features/resource/370505b.pd...

[2] What are the 3-bit field choices for Hw_Arm_Sel in PCI-6601?
https://forums.ni.com/t5/Driver-Development-Kit-DDK/What-are-the-3-bit-field-choices-for-Hw-Arm-Sel-...
 

[ItaiH]

Hello Joe.

Thank you for your answers.

Itai

[ItaiH]

Hello Joe!

"If you write 0d3 (0b10) to the Output_Select field, the line will be programmed as digital output."

we beleive should read: "If you write 0d2 (0b10) to the Output_Select field, the line will be programmed as digital output".

After figuring this out, we successfully programmed a 6602 board to output data from the following PFI lines: 9, 13, 17, 21, 25 & 29 (This is sufficient for now).

We can confirm that it was not necessary to program the TO_StrobeReg and TO_ConfigReg registers.

Note that the 6602 board contains two TIOs, so there exist two TO_InitValReg registers. We used both of these registers (because we were using the I/O Config Registers from both of the TIOs to perform other kind of configuration - Clock Output). We did not try using a single TIO register although we guess it could work this way as well (since there exist a board with a single TIO).

Thank you for your help.

Itai

[JoeFriedchicken]

Excellent! Thanks for outlining your work 🙂

Thanks too for pointing out my typo. To re-word it correctly: setting Output_Select to 0 will put the pin in high-impedance, setting it to 1 will connect it to a counter output, and setting it to 2 will connect it to a digital output; 3 is undefined.