Manual PCI enumeration

[tkreider]

I have the HDDK. I've read the 'manuals'.

My application requires me to enumerate the PCI bus manually. My OS (VxWorks) does not enumerate the PCI bus for me.
My issue is that the manuals for the NI hardware assumes that the OS has done bus enumeration. The examples assumes that the cards are set up and given address space to work with (on Windows/Mac).
Normal enumeration by hand seems to leave me with a card that won't react to DIO commands as issued by the examples.

Question: Where is the complete documentation for the NI MITE chip? What is with this 0xAEAE write to BAR0+0x340? What am I missing documentation wise (and don't say 'get the hddk')?

Thanks

[tkreider]

Follow-up, here's what I've tried...

PCI-6508, Configuration base address : 0x4000000

Write (0x4000010) = 0x8000000 // set BAR0
Write (0x4000014) = 0x10000000 // set BAR1
Write (0x4000002) = 0x00000002 // enable memory windows
Write (0x8000340) = 0x0000AEAE // Undocumented call made in the literature (320938c.pdf, page B12).
Write (0x80000C0) = 0x10000080 // Setting undocumented mystery register in MITE to point to BAR1 AND 0x80.

Write (0x10000003) = 0x80 // btye write to PortA config register for all outputs
Write (0x10000000) = 0x00 // Clear PortA
Write (0x10000000) = 0xFF // Set PortA

At this point the DIO Port A should transition from low to high. It doesn't. What part of the incantation did I miss? Where are the mystery registers defined?

Thom

[gcs]

I'm not very familiar with vxWorks, but you may not need to explicitly set BAR0 and BAR1. The values assigned by the OS may be fine. If this is the case, you can eliminate your first, second, and fourth writes. Of course, your fifth write would need to be modified based on the value of BAR1 assigned by the OS.

Regarding your second write, you should read the value of the command register, or-in the memory access enable, and then write the resulting value rather than blasting the command register with only the memory access enable set.

Hope this helps,

geoff

[tkreider]

Geoff:
Thanks for the speedy reply, I didn't think anyone cruised this site often.

As for my problem, my OS (VxWorks) does not make a single transaction on this bus for me. IE, the devices on this PCI bus are not initialized at all. The BAR's show zero according to the bus analyzer.

Writing the memory enable command with (n OR 2) is a good idea, I forgot that mattered. I'll give it a try.

My real issue, one that I would rather have solved than just getting this to work is: where are all these other registers defined? What exactly is going on with this 0xAEAE write? If I knew these things, I could solve my own problems...

Thanks for the tips!
Thomas

[gcs]

I may be wrong, but I don't believe that the other registers are defined in a public document. The MITE register at offset 0xC0 is somewhat document in the DIO manual you referenced; the comment on page B-15 states "activate the standard i/o window." Yes, I realize that this isn't as helpful as a bit map. Regarding the MITE register at offset 0x340, I would not write to that register. If you look at the example on pages B-14 to B-15, you'll notice that register is not involved. Hopefully, if I'm wrong regarding the availability of additional documentation, someone will correct me.